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Appendix D: Open Host Controller

Endpoint Descriptors

Endpoint descriptors exist for every endpoint on the USB and provide information related to the location (device address and endpoint number) and characteristic of the endpoint. In addition, the ED contains pointers to the TD list when there have been transfers enqueued by the OHCD. Figure D-5 illustrates the format of the ED, and Table D-1 through Table D-4 define each bit field within the descriptor.

Figure D-5: Endpoint Descriptor Format

31

26

16

15 14 13 12 11 10

7

6

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

--------

 

MPS

F

K

S

D

 

EN

 

FA

 

 

 

 

DW 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

 

3

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transfer Descriptor QueueailT Pointer (TailP)

 

 

 

--------

 

 

DW 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DW 2

 

 

 

 

Transfer Descriptor Queue HeadointerP (HeadP)

 

 

0

C

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

 

3

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DW 3

 

 

 

 

 

Next Endpoint Descriptor (NextED)

 

 

 

--------

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table D-1: Definition of Endpoint Descriptor Fields (DW0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

Field Name

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6:0

 

FA

Device Address — USB device containing the target endpoint.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10:7

 

EN

Endpoint Number — Address of target endpoint within

 

 

 

 

 

 

device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

483

USB System Architecture

Table D-1: Definition of Endpoint Descriptor Fields (DW0)

Bit

Field Name

Description

 

 

 

 

 

 

 

 

 

12:11

D

Direction — Direction of transfer, encoded as follows:

 

 

 

00b = get direction from TD

 

 

 

01b = OUT

 

 

 

10b = IN

 

 

 

11b = get direction from TC

 

 

 

 

 

13

S

Speed — Specifies cable speed of the endpoint.

 

 

 

0 = full speed (12 Mb/s)

 

 

 

1 = low speed (1.5 Mb/s)

 

 

 

 

 

14

K

Skip — When set the host controller continues to the next ED

 

 

 

without processing any TDs associated with this ED.

 

 

 

 

 

15

F

Format — Defines the format of the TDs linked to this ED.

 

 

 

0 = interrupt, bulk, or control TD format

 

 

 

1 = isochronous TD format

 

 

 

 

 

26:16

MPS

Maximum Packet Size — Specifies the maximum packet size

 

 

 

supported by this endpoint.

 

 

 

 

 

 

Table D-2: Definition of Endpoint Descriptor Fields (DW1)

 

 

 

 

 

Bit

Field Name

Description

 

 

 

 

 

 

 

 

 

3:0

“-------”

Not Defined — These fields can be used by the host controller

 

 

 

driver for any purpose, and are ignored by the host controller.

 

 

 

 

 

31:4

TailP

Transfer Descriptor Queue Tail Pointer — Points to the last TD

 

 

 

in the queue associated with this ED. If TailP and HeadP are

 

 

 

the same value, then the ED contains no TDs that the host con-

 

 

 

troller can process. If they are different values, the TDs specify

 

 

 

a valid memory buffer to transfer information to or from.

 

 

 

 

 

484

Appendix D: Open Host Controller

Table D-3: Definition of Endpoint Descriptor Fields (DW2)

Bit

Field Name

Description

 

 

 

 

 

 

0

H

Halted — When set, this bit indicates that processing of the TD

 

 

queue has halted, usually due to an error incurred when pro-

 

 

cessing the TD queue.

 

 

 

1

C

Toggle Carry — This bit contains the value of the toggle bit

 

 

when it must be transferred from one TD to the next.

 

 

 

2

0

A field with zero must be written as a zero by the host control-

 

 

ler driver.

 

 

 

31:4

HeadP

Transfer Descriptor Queue Head Pointer — Points to the next

 

 

TD in the list to be processed for this endpoint.

 

 

 

 

Table D-4: Definition of Endpoint Descriptor Fields (DW3)

 

 

 

Bit

Field Name

Description

 

 

 

 

 

 

3:0

“-------”

Not Defined — These fields can be used by the host controller

 

 

driver for any purpose, and are ignored by the host controller.

 

 

 

31:4

NextED

Next Endpoint Descriptor Pointer — Points to next ED descrip-

 

 

tor in the linked list. If zero, this indicates the end of the linked

 

 

list.

 

 

 

Transfer Descriptors

Transfer descriptors are enqueued when an IRP is transferred to the OHCD. The TD contains the specific information needed to perform the transfer, such as the memory buffer location where OUT data resides or where IN data will be placed. A given transfer will likely take numerous frames to complete, and completion status is reported in the TD. Two forms of transfer descriptor are defined:

General TD

Isochronous TD

485

USB System Architecture

The general TD is used for all transfers other than isochronous. Device drivers that support isochronous transfers typically request additional transfers before the first has completed, and these drivers may also provide buffering so that data rate matching can be performed. The isochronous TDs support this mechanism.

General Transfer Descriptor

The general TD format is illustrated in Figure D-6, and the content of each field is defined in Table D-5 on page 486 through Table D-8 on page 488.

Figure D-6: Transfer Descriptor Format

31 30 29 28 27 26 25 24 23

 

21 20 19 18 17

 

 

 

0

 

 

CC

EC

T

 

DI

 

DP

R

 

--------

 

 

 

DW 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Current BufferointerP (CBP)

 

 

 

 

DW 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

4

3

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DW 2

 

 

 

 

 

 

 

Next TD Pointer (NextTD)

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Buffer End (BE)

 

 

 

 

DW 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table D-5: Definition of Transfer Descriptor Fields (DW0)

Bit

Field Name

Description

 

 

 

 

 

 

17:0

“-------”

Not Defined — These fields can be used by the host controller

 

 

driver for any purpose, and are ignored by the host controller.

 

 

 

486

 

 

Appendix D: Open Host Controller

 

 

 

 

Table D-5: Definition of Transfer Descriptor Fields (DW0)

 

 

 

Bit

Field Name

Description

 

 

 

 

 

 

18

R

Buffer Rounding — If zero, this bit specifies that the last data

 

 

packet from an endpoint must exactly fill the defined data

 

 

buffer. If one, then the last data packet may be smaller than the

 

 

defined buffer without causing an error condition.

 

 

 

20:19

DP

Direction/PID — The Packet ID is for this transfer is specified

 

 

within this field, which also defines the direction of transfer.

 

 

The field is encoded as follows:

 

 

00b = Setup (to endpoint)

 

 

01b = OUT (to endpoint)

 

 

10b = IN (from endpoint)

 

 

11b = Reserved

 

 

 

23:21

DI

Delay Interrupt — Contains a delay count that specifies the

 

 

number of frames that the host controller must wait before gen-

 

 

erating an interrupt, indicating that the TD has completed suc-

 

 

cessfully. If this field contains “111b,” then there is no interrupt

 

 

associated with completing the TD.

 

 

 

25:24

T

Data Toggle — The least significant bit of this field contains the

 

 

data toggle state. This value is only valid when the most signif-

 

 

icant bit of this field is “1.” If the msb of this field is “0,” then

 

 

the toggle bit must be obtained from the Toggle Carry within

 

 

the ED.

 

 

 

27:26

EC

Error Count — This field contains the error count associated

 

 

with transaction errors that have occurred when processing

 

 

this transfer descriptor. This field is incremented each time a

 

 

transmission error occurs. When the value increments to three,

 

 

the error type is recorded in the error condition code field (bits

 

 

31:28) and the endpoint is halted. When the TD completes

 

 

before three errors occur, this field is reset to zeros.

 

 

 

31:28

CC

Error Condition Code — Specifies the type of error that has

 

 

occurred when executing this TD.

 

 

 

487

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