Chapter 5: LS/FS Signaling Environment

Hub Driver Characteristics

All downstream facing hub ports must support low-speed driver characteristics as well as full-speed driver characteristics. This is necessary because either a low-speed device or a high-speed device may be attached to a given port.

Differential Receivers

USB differential amplifiers must feature an input sensitivity of 200mV when both differential data inputs are in the range of at least 0.8V to 2.5V with respect to local ground. This input sensitivity reduces noise generated by the buffers themselves.

Start of Packet (SOP)

Each packet begins with a synchronization sequence of 8 bits. This synchronization sequence is used as a receive clock and allows a Phase Lock Loop (PLL) or a Delay Lock Loop (DLL) to establish synchronization with the incoming packet. Prior to the arrival of a packet, the cable and interface are in their idle state (J state). The first transition of the synchronization sequence is to the K state, which is the indication of an incoming packet. Figure 5-15 illustrates the synchronization sequence and the SOP.

Figure 5-15: Start of Packet Is Recognized at the Beginning of the Synchronization Sequence

9,+ PLQ 9GF

9,/ PD[ 9GF

92/ PD[ 9GF 966

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USB System Architecture

End of Packet (EOP)

End of packet is signalled by a single-ended zero (SE0). The transmitter drives SE0 for 2 bit times (lowor full-speed) at the end of each packet to signal EOP, and the single-ended receivers detect EOP. Figure 5-16 illustrates EOP signaling.

Figure 5-16: Fullor Low-Speed EOP signaling

Single-Ended Receivers

Two single-ended receivers are employed by USB devices to recognize particular bus states (as illustrated in Figure 5-1 on page 95). For example, when both differential data lines are driven low for greater than 2.5µs, a USB device RESET is signaled.

The single-ended receivers each monitor one of the data lines. Normally, the D+ and D- lines are in opposite states due to the pullup resistor on one of the data lines when the bus is idle, and due to the differential signaling when the bus is being actively driven. In these conditions, the differential amplifier will amplify the difference between the two data lines. However, in some instances both data lines are driven low to signal a particular condition. For example, both data lines are driven low for 2 bit times after transmitting a packet of information to signify the end of packet, or EOP. The differential amplifiers in this case will have no output, since there is no potential difference at the inputs of the receiver. The single-ended receiver will be able to detect the EOP state when both D+ and D- are low.

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