Добавил:
Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
USB System Architecture (USB 2.0).pdf
Скачиваний:
173
Добавлен:
03.05.2015
Размер:
7.03 Mб
Скачать

Chapter 12: HS Transfers, Transactions, & Scheduling

Isochronous Transaction Errors

The protocol for isochronous transfers does not include a USB-specific mechanism to verify delivery of data (i.e., no handshake packet verification or data toggle is used). However, packet error checks are performed and reported to the device or application layer in software. Any error recovery must be device-spe- cific.

High-Speed Interrupt Transfers

The high-speed interrupt transfers provide the ability to perform high-band- width operations as do isochronous transfers, but unlike isochronous transfers, USB verifies whether data transfers have completed successfully via handshake packets. This gives designers the capability to implement devices that require both guaranteed bandwidth and guaranteed data delivery. The following sections detail the characteristics of high-speed interrupt transactions.

Maximum Packet Size

Maximum packet size for high-speed interrupt transfers is increased to 1024 bytes. In contrast interrupt transfers are limited to 64 bytes for full-speed and 8 bytes for low speed.

Interrupt Bandwidth

A single interrupt transaction is permitted per endpoint in the standard implementation. This gives high-speed endpoints the ability to transfer data at a maximum rate of 1024 bytes every frame, or 8MB/s. The overall maximum bandwidth that is available during a frame for interrupt transfers is a function of the:

packet overhead associated with each interrupt transaction

propagation time of each packet (between host and target device)

device response time

size of the data payload

Figure 12-3 on page 248 illustrates the overhead from packets used during an interrupt transaction, and lists the overhead associated with propagation delay. Note that overhead from bit stuffing is not included in the calculation.

247

USB System Architecture

Figure 12-3: Interrupt Transaction Overhead

 

 

 

 

 

2YHUKHDG E\WHV

 

 

 

 

 

 

 

 

 

 

 

 

 

,1 7RNHQ 3DFNHW

 

 

 

 

 

 

 

 

 

 

 

 

 

7\SH )LHOG

 

&KHFN )LHOG

'HYLFH $

 

(QG3RLQW $

 

 

&5&G

 

G

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OVE

PVE OVE

PVE

OVE

PVE OVE

PVE

 

PVE

OVE

 

 

 

 

 

E\WHV

 

 

 

 

$GGU

$GGU (3

(3

 

&5& &5&

 

E\WH PLQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,GOH

6\QF

 

 

 

 

 

 

 

 

 

 

 

 

 

(23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2YHUKHDG'DW 3DFNHW E\WHV

 

 

 

 

7\SH )LHOG

 

 

&KHFN )LHOG

 

 

 

 

 

 

 

 

 

 

OVE

PVE

OVE

PVE OVE

 

 

E\WHV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,GOH

6\QF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

'DWD )LHOG

 

 

&5&

 

 

 

 

%\WHV

PVE

PVE

OVE

 

 

&5& &5&

 

 

 

E\WH PLQ (23

 

 

 

2YHUKHDG

E\WHV

 

 

7RWDO 3DFNHW RYHUKHDG

 

 

 

 

$FN 3DFNHW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E\WHV

 

 

 

 

 

 

7\SH )LHOG

 

 

&KHFN )LHOG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OVE

PVE

 

OVE

PVE

 

 

 

 

 

 

 

 

E\WHV

 

 

 

 

 

E\WH PLQ

,QWHUUXSW 7UDQVIHU 2YHUKHDG

,GOH

6\QF

 

 

 

 

 

(23

 

 

3DFNHW RYHUKHDG

E\WHV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,QWHUSDFNHW GHOD\

E\WHV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7RWDO RYHUKHDG

E\WHV

Table 12-2 on page 249 lists the maximum throughput of HS interrupt transactions within a given microframe. The table provides the following information:

Column 1 — gives a variety of example payload sizes from 1 byte up to the maximum packet size of 1024 bytes.

Column 2 — gives the percentage of bus bandwidth taken by a single transaction when the payload is of the size specified in column 1.

Column 3 — gives the theoretical number of interrupt transactions that could be completed in a single microframe. These additional transactions could only be performed in the event that the same number of additional endpoints were being accessed during the same microframe.

Column 4 — gives the maximum bandwidth that could be consumed by interrupt transactions in a given microframe.

248

Соседние файлы в предмете [НЕСОРТИРОВАННОЕ]