USB System Architecture

Figure 5-8: Signaling State During Device Disconnect

Bus Idle

The idle state of the bus depends on whether a lowor full-speed device is attached. Figure 5-9 on page 103 illustrates the bus idle condition for both LS

and FS devices. Bus idle is valid when D+ (D-) is pulled up to the VIHZ level (2.7V minimum to 3.6V maximum) and D- (D+) is pulled below 0.8V.

Since FS and LS bus idle are reflected with opposite line states, the hub must invert signaling to low-speed devices, because all packets are received from the host using full speed signal states (because the hub is a full-speed device). If full-speed packets are repeated to low-speed ports without inversion, the signaling states will be misinterpreted by the physical layer of the low-speed device that has a pull-up on D-.

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Chapter 5: LS/FS Signaling Environment

Figure 5-9: Bus Idle Line States

Device RESET

A device is reset under host software control once it has been detected. This forces a device into its default state, which is required prior to configuration. RESET is signaled by the hub port interface by driving a single-ended zero (SE0). Figure 5-10 on page 104 illustrates the signal states and timing requirements for signaling RESET. Note that the duration of RESET is defined by TDRST (10ms min. and 20ms max.) and applies to USB hubs that receive a “SetPortRe-

set” request. Root hubs drive RESET for the duration specified by the TDRSTR parameter (50ms min.). Devices are required to detect RESET within the TDE-

TRST timing parameter (2.5 s min. to 10ms max.).

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