USB System Architecture

Table D-12: Definition of Isochronous Transfer Descriptor Fields (DW3)

The Open Host Controller Registers

The OHC registers are mapped into PCI memory address space via the PCI configuration base address register. These registers can be grouped into functional groups as follows and as illustrated in Figure D-8:

Host Controller Control and Status — these registers define the operating mode of the host controller, reflect current status of the host controller, provide interrupt control and status, and reflect error status conditions.

Memory Pointers — these registers provide pointers to the data structure that are required to communicate with the host controller driver and perform transactions based on the transfer descriptors that reside in memory.

Frame Counter and Control — frame timing status and control are provided by this set of registers, and govern SOF timing and control events that are tied to frame timing intervals.

Root Hub Status and Control — these registers are dedicated to the root hub function. Two sets of registers are included to control the two ports.

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Appendix D: Open Host Controller

Please refer to the open host controller specification for a detailed description of these registers.

Figure D-8: Open Host Controller Registers

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USB System Architecture

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