Chapter 8: Error Recovery

The host in this case needs to know when it’s safe to transmit the next packet. Since the EOP detection was premature, the target may continue to transmit data. If the host detects no additional bus transitions within the bus time-out period of 16 bit times, it can safely assume that no more data will be sent by the target. The host can then safely transmit the next packet and be assured of no collisions on the bus. If, however, bus transitions continue, the host must wait for the EOP, and then wait for 16 bit times before transmitting the next packet. Note that the 16 bit time delay is required to ensure that the target detects that the host has not responded (i.e., the target time-out counter expires). This ensures that the target recognizes that the packet transfer has failed.

Data Toggle Errors

Data toggle is a mechanism used to ensure that the transmitter and receiver of a transfer remain synchronized throughout a long transfer requiring a large number of individual transactions. Data toggle solves the problem associated with corrupted handshake packets, as described in the section entitled “Handshake Packet Errors” on page 172.

Data Toggle Procedure Without Errors

Data toggle is supported for interrupt, bulk, and control transfers only. The transmitter and receiver involved in a transfer that supports the data toggle mechanism must implement toggle bits. The transmitting device and receiving device both transition their toggle bits to the opposite state when they both agree that the transaction has occurred without error. The two data packet types (DATA0 and DATA1) are transmitted alternately and compared by the receiver of the packet to verify that the correct packet has been received. The transmitter uses the data packet type that matches the current state of its toggle bit (e.g., if the toggle bit = 0, then DATA0 is used). To explain the concept of the data toggle mechanism, consider the following transactions that are described and illustrated in the following sections.

Data Toggle during OUT Transactions

Figure 8-3 on page 177 illustrates the packet sequence and toggle bit transitions for bulk data transfer from the host to a target device. Assume that the toggle bits in the transmitter and receiver are initially cleared (zero). The transfer proceeds as follows:

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Transaction 1

1.The host transmits an OUT token to the target device.

2.The target device receives the token without any packet errors.

3.The host then transmits a DATA0 packet (consistent with its toggle bit) to the target device.

4.The target receives DATA0, which matches the toggle bit.

5.Having successfully received the DATA0 packet, the toggle bit transitions to one.

6.The target transmits an ACK handshake packet to inform the host that data was received without error.

7.The host receives the ACK packet without error.

8.Having successfully received the ACK packet, the host transitions the toggle bit to one.

Transaction 2

1.The next transaction to the target begins with the OUT token transmitted to the target.

2.The target device receives the OUT token without errors.

3.The host transmits a DATA1 packet (consistent with its toggle bit).

4.The target receives the packet without error and DATA1 matches the state of its toggle bit.

5.Having successfully received the DATA1 packet, the receiver toggles the bit to zero.

6.The target transmits an ACK handshake packet to inform the host that data was received without error.

7.The host receives the ACK packet without error.

8.Having successfully received the ACK packet, the host transitions the toggle bit to a zero.

This procedure is performed for each transaction until the entire transfer completes. As long as the data packet received matches the toggle bit and the transmitter receives the ACK without error, the transmitter and receiver remain in synchronization.

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Chapter 8: Error Recovery

Figure 8-3: OUT Transaction With Data Toggle Sequence and No Errors

Transaction 1

Transaction 2

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Data Toggle During IN Transactions

Figure 8-4 illustrates the sequence of two IN transactions and the transitions that would take place during an error-free transfer. The sequence occurs as follows:

Transaction 1

1.The host transmits an IN token to the target device.

2.The target device receives the token without errors.

3.The receiver then returns a DATA0 packet (consistent with the state of the toggle bit) to the host.

4.The host receives DATA0, which matches its toggle bit.

5.Having successfully received the DATA0 packet, the toggle bit transitions to one.

6.The host transmits an ACK handshake packet to inform the target that it received the data packet without error.

7.The target receives the ACK packet without error.

8.Having successfully received the ACK packet, the target transitions its toggle bit to one.

Transaction 2

1.The next transaction to the target begins with an IN token transmitted to the target.

2.The target device receives the IN token without errors.

3.The target returns a DATA1 packet (consistent with the state of its toggle bit).

4.The host receives the DATA1 packet without errors and it correctly matches the host’s toggle bit.

5.Having successfully received the DATA1 packet, the host toggles the bit to zero.

6.The host transmits an ACK handshake packet to inform the target that it has received the data packet without errors.

7.The host receives the ACK packet without errors.

8.Having successfully received the ACK packet, the host transitions the toggle bit to zero.

This procedure is performed for each transaction until the entire transfer completes. As long as the data packet received matches the toggle bit and the transmitter receives the ACK without error, the transmitter and receiver remain in synchronization.

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