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Chapter 5: LS/FS Signaling Environment

NRZI Encoding

USB data packets are encoded using NRZI (Non-Return to Zero, Inverted). Figure 5-17 illustrates the steps involved in transferring information across a USB cable segment. NRZI encoding is performed first by the USB agent that is sending information. Next, the encoded data is driven onto the USB cable by the differential driver. The receiver amplifies the incoming differential data and delivers the NRZI data to the decoder. Encoding and differential signaling are used to help ensure data integrity and eliminate noise problems.

Figure 5-17: Transfers Across USB Cables Employ NRZI Encoding and Differential Signaling

 

 

&DEOH

 

 

15=,

'LIIHUHQWLDO

6HJPHQW

'LIIHUHQWLDO

15=,

(QFRGHU

'ULYHU

<

5HFHLYHU

'HFRGHU

 

 

 

 

 

 

D+

 

 

 

 

D-

 

 

Data transferred via the USB is encoded using NRZI encoding to help ensure integrity of data delivery, without requiring a separate clock signal be delivered with the data. NRZI is by no means a new encoding scheme. It has been used for decades in a wide variety of applications. Figure 5-18 illustrates a serial data stream and the resulting NRZI data. Zero’s in the NRZI data stream are represented by transitions while 1s are represented by the absence of a transition. The NRZI encoder must maintain synchronization with the incoming data stream to correctly sample the data. The NRZI data stream must be sampled within a data window to detect whether a transition has occurred since the previous bit time. The decoder samples the data stream during each bit time to check for transitions.

111

USB System Architecture

Figure 5-18: NRZI Encoded Data

Idle

0

1

1

0

1

0

0

0

1

1

1

0

1

0

Data

NRZI

Transitions in the data stream permit the decoder to maintain synchronization with the incoming data, thereby eliminating the need for a separate clock signal. Note however that a long string of consecutive 1s results in no transitions, causing the receiver to eventually lose synchronization. The solution is to employ bit stuffing.

Bit Stuffing

Bit stuffing forces transitions into the NRZI data stream in the event that six consecutive 1s are transmitted. This ensures that the receiver detects a transition in the NRZI data stream at least every seventh bit time. This enables the receiver to maintain synchronization with the incoming data. The transmitter of NRZI data is responsible for inserting a 0 (stuffed bit) into the NRZI stream. The receiver must be designed to expect an automatic transition following six consecutive 1s and discard the 0 bit that immediately follows the sixth consecutive 1.

The top line in Figure 5-19 illustrates raw data being delivered to the receiver. Note that the data stream contains a string of eight consecutive 1s. The second line represents the raw data with the stuffed bits added. A stuffed bit is inserted between the sixth and seventh 1s in the raw data stream. Delivery of the seventh 1 is delayed by one data time so that the stuffed bit can be inserted. The receiver knows that the bit following the sixth consecutive 1 will be a stuffed bit (0), causing it to be ignored. Note that if the seventh bit in the raw data was a 0, the stuffed bit would still be inserted in the same location, resulting in two consecutive 0s in the stuffed data stream.

112

Chapter 5: LS/FS Signaling Environment

Figure 5-19: Stuffed Bit

 

Idle 0 0 0 1 1 1 1 1 1 1 1 0 1 1

Data

 

 

Stuffed

 

 

Bit

Stuffed

Data

NRZI

0

0

1

1

1

1

1

1

0

1

1

0

1

1

0

Receiver discards stuffed bi t

Summary of USB Signaling States

Table 5-2 summarizes all of the USB signaling states. The first column identifies the state, column two defines the related signaling condition at the driver, and column three defines the receiver’s state.

Table 5-2: USB Bus States

Bus

Signaling Levels

State

 

 

From Originating Driver

At Receiver

 

 

 

 

 

 

 

Differential “1”

D+ > VOH (min) and

(D+) - (D-) > 200mV and

 

D- < VOL (max)

D+ > VIH (min)

Differential “0”

D- > VOH (min) and

(D-) - (D+) > 200mV and

 

D+ < VOL (max)

D- > VIH (min)

Single-ended 0 (SE0)

D+ and D- < VOL (max)

D+ and D- < VIL (max)

 

 

 

Data J State:

 

 

Low Speed

Differential “0”

Full Speed

Differential “1”

 

 

 

113

USB System Architecture

Table 5-2: USB Bus States

Bus

Signaling Levels

State

 

 

From Originating Driver

At Receiver

 

 

 

 

 

 

 

Data K State:

 

 

Low Speed

Differential “1”

Full Speed

Differential “0”

 

 

 

Low Speed Idle

NA

D- > VIHZ (min) and

 

 

D+ < VIL (max)

Full Speed Idle

NA

D+ > VIHZ (min) and

D- < VIL (max)

 

 

Resume State:

Data K State

 

 

Start of Packet

Data lines switch from idle to K state

(SOP)

 

 

 

 

 

End of Packet

SE0 for 2 bit times followed

SE0 for equal to or greater

(EOP)

by a J state for 1 bit time

than 1 bit time followed by

 

 

a J state for 1 bit time

 

 

 

Disconnect

NA

SE0 for equal to or greater

(Upstream only)

 

than 2.5 s

Connect

NA

Idle for equal to or greater

(Upstream only)

 

than 2.5 s

Reset

D+ and D- < VSE for 10ms

SE0 for equal to or greater

(Downstream only)

 

than 2.5 s

Figure 5-20 illustrates the signal levels used for the USB. Note that USB uses 3.3Vdc signaling levels.

114

Chapter 5: LS/FS Signaling Environment

Figure 5-20: USB Signaling Levels

VOH(max)

3.6 Vdc

VOH (min)

2.8 Vdc

VSE (max)

2.0 Vdc

VSE (min)

0.8 Vdc

VOL (max)

0.3 Vdc

VSS

 

115

USB System Architecture

116

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