Digital design with CPLD applications and VHDL (R. Dueck, 2000)

quad4to1.scf

ARCHITECTURE mux4 OF quad4to1 IS BEGIN

–— Selected Signal Assignment MUX4: WITH s SELECT

y <= d0 WHEN 0, d1 WHEN 1, d2 WHEN 2, d3 WHEN 3;

END mux4;

Figure 5.41 shows a set of simulation waveforms for the multiplexer. The D inputs are shown in groups of four, the value of each shown as a steady hexadecimal value. The select inputs are grouped, showing an increasing 2-bit binary count as a hexadecimal value (0 to 3, then repeating). As the S inputs select each group of D inputs, their combined value is directed to the Y output group.

waveforms from bottom to top, you will see that they generate a repeating binary sequence (000, 001, 010, 011, 100, 101, 110, 111, 000 . . .).

S1

S0

Q0

FIGURE 5.43

Time-Dependent Selection of Eight Multiplexer Channels

If we connect the counter outputs Q2Q1Q0 to the select inputs of an 8-to-1 MUX, as in Figure 5.43, we will select the channels in sequence, one after the other. The counter is labelled CTR DIV 8 because its most significant bit output has a frequency equal to the clock frequency divided by eight. The triangle on the clock input indicates that it is active when the clock waveform makes a transition from one logic level to another. Since there is no inverting bubble on the clock input, we know that the active clock transition is from LOW to HIGH (i.e., a positive edge).

Waveform Generation. A multiplexer and counter can be used as a programmable waveform generator. The output waveform can be programmed to any pattern by switching the logic levels on the data inputs. This is an easy way to generate an asymmetrical waveform, a task which is more complicated using other digital circuits. The circuit can also generate symmetrical waveforms by alternating the logic levels of consecutive groups of inputs.

Solution Figure 5.44a shows the waveform generator circuit. The output waveform with respect to the counter inputs is shown in Figure 5.44b. This pattern is relatively difficult to generate by other means since it has several unequal HIGH and LOW sequences in one period.

Q0

Q1

Q2

Y

How should the switches be set to generate a symmetrical 2 kHz waveform? A symmetrical 4 kHz waveform?

Solution

Pattern for 2 kHz:

Pattern for 4 kHz:

Time Division Multiplexing

K E Y T E R M S

Time division multiplexing (TDM) A technique of using one transmission line to send many signals simultaneously by making them share the line for equal fractions of time.

Time slot A period of time during which a transmitted data element has sole access to a transmission path.

Bit multiplexing A TDM technique in which one bit is sent from each channel during the channel’s assigned time slot.

Byte (or word) multiplexing A TDM technique in which a byte (or word) is sent from each channel during its assigned time slot. (A byte is eight bits; a word is a group of bits whose size varies with the particular system.)

Time division multiplexing is a method of improving the efficiency of a transmission system by sharing one transmission path among many signals. For example, if we wish to send four 4-bit numbers over a single transmission line, we can transmit the bits one after the other, as shown in Figure 5.45.

FIGURE 5.45

4 4 Data Stream (Bit Multiplexing)

In Figure 5.45, we see the least significant bit of the 4-bit word p0 transmitted, followed by the LSB of p1, p2, then p3. After that, the second bit of each word is transmitted in sequence, then all the third bits, and finally, all MSBs in sequence. Each bit is assigned a time slot in the sequence. During that time, the bit has sole access to the transmission line. When its time elapses, the next bit is sent and so on in sequence, until the channel assignment returns to the original location. This technique, known as bit multiplexing, can be implemented by a circuit similar to the waveform generator shown in Figure 5.44. Rather than fixed switch inputs, the data inputs would be some data source, such as a digitized audio signal.

We can also arrange our circuit so that one byte (8 bits) or one word (a group of bits) is sent through a selected channel. In this case, we must keep the channel selected for enough clock pulses to transmit the byte or word, then move to the next one. This technique is called byte (or word) multiplexing. Figure 5.46 shows a data stream of four 4-bit words that are word-multiplexed down a data transmission path.

FIGURE 5.46

4 4 Data Stream (Word Multiplexing)

d(1) WHEN “001”,

d(2) WHEN “010”,

d(3) WHEN “011”,

d(4) WHEN “100”,

d(5) WHEN “101”,

d(6) WHEN “110”,

d(7) WHEN “111”;

END a;

The simulation is shown in Figure 5.48. For clarity, digital data are present on the MUX inputs just before and after they are switched to the Y output. The output shows the channel data in sequence, starting with channel 0.

FIGURE 5.48

Simulation for an 8-bit Time-Division Multiplexer

SECTION 5.3 REVIEW PROBLEM

5.5What defines whether a multiplexer application is time-dependent or not? What additional component can be added to make a MUX application time-dependent?

5.4Demultiplexers

K E Y T E R M S

Demultiplexer A circuit that uses a binary decoder to direct a digital signal from

a single source to one of several destinations.

A demultiplexer performs the reverse function of a multiplexer. A multiplexer (MUX) directs one of several input signals to a single output; a demultiplexer (DMUX) directs a single input signal to one of several outputs. In both cases, the selected input or output is chosen by the state of an internal decoder.

Figure 5.49 shows the logic circuit for a 1-to-4 demultiplexer. Compare this to Figure 5.4, a 4-output decoder. This circuits are the same except that the active-LOW enable input has been changed to an active-HIGH data input. The circuit in Figure 5.49 could still be used as a decoder, except that its enable input would be active-HIGH.

198 C H A P T E R 5 • Combinational Logic Functions

S0

S1

D

Y0

Y1

Y2

Y3

FIGURE 5.49

4-bit Decoder/Demultiplexer

Each AND gate in the demultiplexer enables or inhibits the signal output according to the state of the select inputs, thus directing the data to one of the output lines. For instance, S1S0 10 directs incoming digital data to output Y2.

FIGURE 5.50

Same Device Used as a Decoder or Demultiplexer

Figure 5.50 illustrates the use of a single device as either a decoder or a demultiplexer. In Figure 5.50a, input D is tied HIGH. When an output is selected by S1 and S0, it goes HIGH, acting as a decoder with active-HIGH outputs. In Figure 5.50b, D acts as a demultiplexer data input. The data are directed to the output selected by S1 and S0.

N O T E

Since a single device can be used either way, this implies that any of the VHDL binary decoder designs used in this chapter can also be used as demultiplexers.

A decoder/demultiplexer can have active-LOW outputs, but only if the D input is also active-LOW. This is important because the demultiplexer data must be inverted twice to retain its original logic values.

Demultiplexing a TDM Signal

In Example 5.10, we saw how a multiplexer could be used to send 8 digital channels across a single line, multiplexed over time. Obviously, such a system is not of much value if the signals cannot be sorted out at the receiving end. The received digital data must be demultiplexed and sent to their appropriate destinations.

The VHDL code for the demultiplexer is as follows. (This is the same implementation as a 3-line-to-8-line decoder with an enable input.)

—— dmux8.vhd

—— 1-to-8 demultiplexer/decoder

dmux8.vhd

—— Decoder: set d to ‘0’; outputs are activated by

dmux8.scf

——binary combination of s.

——Demultiplexer: apply data stream to d; data directed to

——y output with subscript same as value of s.

——Outputs and d are active-LOW. DMUX data are inverted twice

——to keep them true.