Digital design with CPLD applications and VHDL (R. Dueck, 2000)

ARCHITECTURE adder OF add4gen IS

——Component declaration COMPONENT full_add

PORT (

a, b, c_in : IN BIT; c_out, sum : OUT BIT);

END COMPONENT;

—— Define a signal for internal carry bits SIGNAL c : BIT_VECTOR (4 downto 0);

BEGIN

c(0) c0; adders:

FOR i IN 1 to 4 GENERATE

adder: full_add PORT MAP (a(i),b(i),c(i-1),c(i),sum(i)); END GENERATE;

c4 c(4); END adder;

The GENERATE statement will create hardware that corresponds to the range of the index variable, i. In this case i goes from 1 to 4, so the statement instantiates four instances of the full adder. Since we have an input carry, an output carry and three internal carries, we must use a 5-bit signal (BIT_VECTOR (4 downto 0)) if we are to include all carry bits in indexed form. The input carry, c0, defined in the entity declaration, is assigned to the vector element c(0). Similarly, the output, c4, is assigned the value of the element c(4).

It is easy to expand the adder width by changing the range of the FOR GENERATE statement. For example, to make an 8-bit adder, we change the vectors to have a width of eight bits. The required VHDL code, shown next, requires the same number of lines of code as the 4-bit adder.

2. Add the 2’s complement of the subtrahend to the minuend:

(Discard carry)

We can easily build a circuit to perform 2’s complement subtraction, using a parallel binary adder and an inverter for each bit of one of the operands. The circuit shown in Figure 6.14 performs the operation (A B).

FIGURE 6.14

2’s Complement Subtractor

The four inverters generate the 1’s complement of B. The parallel adder generates the 2’s complement by adding the carry bit (held at logic 1) to the 1’s complement at the B inputs. Algebraically, this is expressed as:

A B A ( B) A B 1

where B is the 1’s complement of B, and (B 1) is the 2’s complement of B.

SOLUTION Let B be the 1’s complement of B.

Parallel Binary Adder/Subtractor

Figure 6.15 shows a parallel binary adder configured as a programmable adder/subtractor. The Exclusive OR gates work as programmable inverters to pass B to the parallel adder in either true or complement form, as shown in Figure 6.16.

FIGURE 6.15

2’s Complement Adder/Subtractor

FIGURE 6.16

XOR as a Programmable Inverter

The ADD/SUB input is tied to the XOR inverter/buffers and to the carry input of the parallel adder. When ADD/SUB 1, B is complemented and the 1 from the carry input is added to the complement sum. The effect is to subtract (A B). When ADD/SUB 0, the B inputs are presented to the adder in true form and the carry input is 0. This produces an output equivalent to (A B).

This circuit can add or subtract 4-bit signed or unsigned binary numbers.

6.22Write a VHDL file to implement the 4-bit adder/subtractor shown in Figure 6.15. Also create a simulation file to test a representative selection of addition and subtraction operations.

SOLUTION The VHDL file is as follows:

addsub4g.vhd

SIGNAL b_comp : BIT_VECTOR (4 downto 1);

BEGIN

—— add/subtract select to carry input (sub 1 for subtract) c(0) sub;

adders:

FOR i IN 1 to 4 GENERATE

——invert b for subtract (b(i) xor 1),

——do not invert for add (b(i) xor 0) b_comp(i) b(i) xor sub;

adder: full_add PORT MAP (a(i), b_comp(i), c(i-1), c(i),

sum(i));

END GENERATE; c4 c(4);

END adder;

The SOP Boolean expression for the overflow detector is:

V SA SB S SA SB S

Figure 6.20 shows a logic circuit that will detect a sign bit overflow in a parallel binary adder. The inputs SA, SB, and S are the MSBs of the adder A and B inputs and outputs, respectively.

FIGURE 6.21

Example 6.24 8-Bit Adder With Overflow Detector

SECTION 6.6B REVIEW PROBLEM

6.10What is the permissible range of values of a sum or difference, x, in a 12-bit parallel binary adder if it is written as:

a.A signed binary number?

b.An unsigned binary number?

6.7BCD Adders

(This section may be omitted without loss of continuity.)

K E Y T E R M

BCD adder A parallel adder whose output is in groups of 4 bits, each group rep-

resenting a BCD digit.

It is sometimes convenient to have the output of an adder circuit available as a BCD number, particularly if the result is to be displayed numerically. The problem is that most parallel adders have binary outputs, and 6 of the 16 possible 4-bit binary sums—1010 to 1111—are not within the range of the BCD code.

BCD numbers range from 0000 to 1001, or 0 to 9 in decimal. The unsigned binary sum of any two BCD numbers plus an input carry can range from 00000 ( 0000 0000

0) to 10011 ( 1001 1001 1 1910).

For any sum up to 1001, the BCD and binary values are the same. Any sum greater than 1001 must be modified, since it requires a second BCD digit. For example, the binary value of 1910 is 100112. The BCD value of 1910 is 0001 1001BCD. (The most significant digit of a sum of two BCD digits and a carry will never be larger than 1, since the largest

such sum is 1910.)

Table 6.10 shows the complete list of possible binary sums of two BCD digits (A and B) and a carry (C), their decimal equivalents, and their corrected BCD values. The MSD of the BCD sum is shown only as a carry bit, with leading zeros suppressed.

Table 6.10 Binary Sums of Two BCD Digits

and a Carry Bit