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C H A P T E R 6 • Digital Arithmetic and Arithemtic Circuits |
6.32Create a simulation for the 4-bit adder/subtractor with overflow detection (Problem 6.31), using the following representative hexadecimal input values: F 1 10 (carry, but no overflow); 7 1 8 (overflow, but no carry); 8 8 10 (carry and overflow); 0 1 F (result 1).
6.33Modify the VHDL file for the 4-bit parallel binary adder/subtractor (addsub4g.vhd) to include an overflow detection circuit. Use two different methods.
6.34What is the permissible range of values that a sum or difference, x, can have in a 16-bit parallel binary adder if it is written as:
a.A signed binary number
b.An unsigned binary number
Section 6.7 BCD Adders
6.35What is the maximum BCD sum of two 3-digit BCD numbers plus an input carry? How many digits are needed to display the result?
6.36What is the maximum BCD sum of two 4-digit BCD numbers plus an input carry? How many digits are needed to display the result?
6.37Based on the answers to Problems 6.35 and 6.36, formulate a general rule to calculate the maximum BCD sum of two n-digit BCD numbers plus a carry bit.
6.38Derive the Boolean expression for a BCD carry output as a function of the sum of two BCD digits.
6.39Draw the circuit for a binary-to-BCD code converter.
6.40Write a VHDL file to implement a binary-to-BCD code converter for a BCD adder. Use a selected signal assignment or CASE statement.
6.41Write a VHDL file that uses the binary-to-BCD code converter of Problem 6.40 and a 4-bit parallel binary adder as components in a BCD adder.
6.42Write a VHDL file that uses a code converter and parallel adder as components in a design that will add two 2-digit BCD numbers and produce a 21⁄2 digit result.
6.43Draw the block diagram of a circuit that will add two 3-digit BCD numbers and display the result as a series of decimal digits. How many digits will the output display?
A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S
Section 6.1a |
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6.1 |
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6.2 |
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Section 6.1b |
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6.3 |
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6.4 |
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Section 6.3 |
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6.5 |
11100000; |
6.6 |
100000. |
Section 6.4 |
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6.7a |
11701H |
6.7b |
1281H |
Section 6.5
6.8 “True or False: 1/4 1/2”
Section 6.6a
6.9 Figures 6.32 and 6.33 show the propagation paths for the carry bits.
Fast carry: 3 gates
Ripple carry: 8 gates
Section 6.6b
6.10a Signed: 2048 x 2047 (11 magnitude bits, 1 sign bit)
6.10b Unsigned: 0 x 4095 (12 magnitude bits, no sign bit: positive implied)
Section 6.7
6.11 Maximum BCD sum 1001 1001 1001 1001 1001 1001 1 1001 1001 1000BCD 199810. This sum requires a 312 -digit numerical display.
Answers to Section Review Problems |
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a1 |
INPUT |
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OR2 |
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INPUT |
AND2 |
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a3 |
INPUT |
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a4 |
INPUT |
AND2 |
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INPUT |
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AND2 |
c1 |
OUTPUT |
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OR3 |
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c2 |
OUTPUT |
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OR4 |
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OR6 |
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AND3 |
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GND |
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VCC
FIGURE 6.32
Fast Carry from A4/B4 to C4.
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C0
FIGURE 6.33
Ripple Carry from C0 to C4
C H A P T E R 7
Introduction to Sequential Logic
O U T L I N E |
C H A P T E R O B J E C T I V E S |
7.1 Latches |
Upon successful completion of this chapter, you will be able to: |
7.2NAND/NOR Latches • Explain the difference between combinational and sequential circuits.
7.3 Gated Latches |
• Define the set and reset functions of an SR latch. |
7.4Edge-Triggered D • Draw circuits, function tables, and timing diagrams of NAND and NOR
7.5Edge-Triggered JK • Explain the effect of each possible input combination to a NAND and a
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Flip-Flops |
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NOR latch, including set, reset, and no change functions, as well as the am- |
7.6 |
Edge-Triggered T |
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biguous or forbidden input condition. |
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Flip-Flops |
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Design circuit applications that employ NAND and NOR latches. |
7.7 |
Timing Parameters |
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Describe the use of the ENABLE input of a gated SR or D latch as an en- |
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able/inhibit function and as a synchronizing function. |
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Outline the problems involved with using a level-sensitive ENABLE input |
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on a gated SR or D latch. |
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Explain the concept of edge-triggering and why it is an improvement over |
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level-sensitive enabling. |
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Draw circuits, function tables, and timing diagrams of edge-triggered D, |
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JK, and T flip-flops. |
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Describe the toggle function of a JK flip-flop and a T flip-flop. |
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Describe the operation of the asynchronous preset and clear functions of D, |
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JK, and T flip-flops and be able to draw timing diagrams showing their |
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functions. |
• Use MAX PLUS II to create simple circuits and simulations with D latches and D, JK, and T flip-flops.
• Create simple flip-flop designs using VHDL.
The digital circuits studied to this point have all been combinational circuits, that is, circuits whose outputs are functions only of their present inputs. A particular set of input
states will always produce the same output state in a combinational circuit.
276 C H A P T E R 7 • Introduction to Sequential Logic
This chapter will introduce a new category of digital circuitry: the sequential circuit. The output of a sequential circuit is a function both of the present input conditions and the previous conditions of the inputs and/or outputs. The output depends on the sequence in which the inputs are applied.
We will begin our study of sequential circuits by examining the two most basic sequential circuit elements: the latch and the flip-flop, both of which are part of the general class of circuits called bistable multivibrators. These are similar devices, each being used to store a single bit of information indefinitely. The difference between a latch and a flipflop is the condition under which the stored bit is allowed to change.
Latches and flip-flops are also used as integral parts of more complex devices, such as programmable logic devices (PLDs), usually when an input or output state must be stored.
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7.1 Latches
K E Y T E R M S
Sequential circuit A digital circuit whose output depends not only on the present combination of inputs, but also on the history of the circuit.
Latch A sequential circuit with two inputs called SET and RESET, which make the latch store a logic 0 (reset) or 1 (set) until actively changed.
SET 1. The stored HIGH state of a latch circuit.
2. A latch input that makes the latch store a logic 1.
RESET 1. The stored LOW state of a latch circuit.
2. A latch input that makes the latch store a logic 0.
All the circuits we have seen up to this point have been combinational circuits. That is, their present outputs depend only on their present inputs. The output state of a combinational circuit results only from a combination of input logic states.
The other major class of digital circuits isthe sequential circuit. The present outputs of a sequential circuit depend not only on its present inputs, but also on its past input states.
The simplest sequential circuit is the SR latch, whose logic symbol is shown in Figure 7.1a. The latch has two inputs, SET (S) and RESET (R), and two complementary outputs, Q and Q. If the latch is operating normally, the outputs are always in opposite logic states.
FIGURE 7.1
SR Latch (Active HIGH Inputs)
The latch operates like a momentary-contact pushbutton with START and STOP functions, shown in Figure 7.2. A momentary-contact switch operates only when it is held down. When released, a spring returns the switch to its rest position.
Suppose the switch in Figure 7.2 is used to control a motor starter. When you push the START button, the motor begins to run. Releasing the START switch does not turn the motor off; that can be done only by pressing the STOP button. If the motor is running,
278 C H A P T E R 7 • Introduction to Sequential Logic
SOLUTION The Q and Q waveforms are shown in Figure 7.3. Note that the outputs respond only to the first set or reset command in a sequence of several pulses.
EXAMPLE 7.2 |
Figure 7.4 shows a latching HOLD circuit for an electronic telephone. When HIGH, the |
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HOLD output allows you to replace the handset without disconnecting a call in progress. |
FIGURE 7.4
Example 7.2
Latching HOLD Button
The two-position switch is the telephone’s hook switch (the switch the handset pushes down when you hang up), shown in the off-hook (in-use) position. The normally closed pushbutton is a momentary-contact switch used as a HOLD button. The circuit is such that the HOLD button does not need to be held down to keep the HOLD active. The latch “remembers” that the switch was pressed, until told to “forget” by the reset function.
Describe the sequence of events that will place a caller on hold and return the call from hold. Also draw timing diagrams showing the waveforms at the HOLD input, hook switch inputs, S input, and HOLD output for one hold-and-return sequence. (HOLD output 1 means the call is on hold.)
SOLUTION To place a call on hold, we must set the latch. We can do so if we press and hold the HOLD switch, then the hook switch. This combines two HIGHs—one from the HOLD switch and one from the on-hook position of the hook switch—into the AND gate, making S 1 and R 0. Note the sequence of events: press HOLD, hang up, release HOLD. The S input is HIGH only as long as the HOLD button is pressed. The handset can be kept on-hook and the HOLD button released. The latch stays set, as S R 0 (neither SET not RESET active) as long as the handset is on-hook.
To restore a call, lift the handset. This places the hook switch into the off-hook position and now S 0 and R 1, which resets the latch and turns off the HOLD condition.
Figure 7.5 shows the timing diagram for the sequence described.
FIGURE 7.5
Example 7.2
HOLD Timing Diagram
7.2 • NAND/NOR Latches |
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SECTION 7.1 REVIEW PROBLEM
7.1A latch with active-HIGH S and R inputs is initially set. R is pulsed HIGH three times, with S 0. Describe how the latch responds.
7.2NAND/NOR Latches
An SR latch is easy to build with logic gates. Figure 7.6 shows two such circuits, one made from NOR gates and one from NANDs. The NAND gates in the second circuit are drawn in DeMorgan equivalent form.
FIGURE 7.6
SR Latch Circuits
The two circuits both have the following three features:
1.OR-shaped gates
2.Logic level inversion between the gate input and output
3.Feedback from the output of one gate to an input of the opposite gate
During our examination of the NAND and NOR latches, we will discover why these features are important.
A significant difference between the NAND and NOR latches is the placement of SET and RESET inputs with respect to the Q and Q outputs. Once we define which output is Q and which is Q, the locations of the SET and RESET inputs are automatically defined.
In a NOR latch, the gates have active-HIGH inputs and active-LOW outputs. When the input to the Q gate is HIGH, Q 0, since either input HIGH makes the output LOW. Therefore, this input must be the RESET input. By default, the other is the SET input.
In a NAND latch, the gate inputs are active LOW (in DeMorgan equivalent form) and the outputs are active HIGH. A LOW input on the Q gate makes Q 1. This, therefore, is the SET input, and the other gate input is RESET.
Since the NAND and NOR latch circuits have two binary inputs, there are four possible input states. Table 7.1 summarizes the action of each latch for each input combination. The functions are the same for each circuit, but they are activated by opposite logic levels.
Table 7.1 NOR and NAND Latch Functions
S |
R |
Action (NOR Latch) |
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Action (NAND Latch) |
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0 |
0 |
Neither SET nor RESET |
0 |
0 |
Both SET and RESET |
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active; output does not |
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active; forbidden condi- |
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change from previous |
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tion |
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state |
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0 |
1 |
RESET input active |
0 |
1 |
SET input active |
1 |
0 |
SET input active |
1 |
0 |
RESET input active |
1 |
1 |
Both SET and RESET |
1 |
1 |
Neither SET nor RESET |
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active; forbidden condi- |
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active; output does not |
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tion |
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change from previous |
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