Digital design with CPLD applications and VHDL (R. Dueck, 2000)

280 C H A P T E R 7 • Introduction to Sequential Logic

We will examine the NAND latch circuit for each of the input conditions in Table 7.1.

The analysis of a NOR latch is similar and will be left as an exercise.

NAND Latch Operation

Figure 7.7 shows a NAND latch in its two possible stable states. In each case the inputs S and R are both HIGH (inactive).

FIGURE 7.7

NAND Latch Stable States

Figure 7.7a shows the latch in its SET condition (Q 1). The feedback connections from each gate output to the input of the opposite gate keep the latch in a stable condition. The upper gate has a LOW on the “inner” input. Since, for a NAND gate, either input LOW makes the output HIGH, this makes Q 1. This HIGH value is fed to the gate on the other side of the latch. The lower gate has both inputs HIGH, thus keeping its output LOW. The LOW at Q feeds back to the upper gate, forming a closed loop of consistent logic levels. There is no tendency for the outputs to change under these conditions.

Figure 7.7b shows a similar state for the latch in a RESET condition (Q 0). As with the SET state, the stability of the latch depends on the feedback connections. The logic values of the latch gate inputs are the same as before, except that the LOW input is on the lower gate, not the upper gate as in the SET condition.

Figure 7.8 shows a NAND latch as a Graphic Design File created with MAX PLUS II. The inputs are labeled nS and nR and one output as nQ as we cannot enter input names with bars over them. (BOR2 “Bubbled OR, 2-inputs”.)

Q

BOR2

OUTPUT

nR

FIGURE 7.8

Graphic Design File representation of a NAND Latch.

N O T E

The documentation for MAX PLUS II recommends that you do not create your own latch circuits or similar cross-coupled structures. Rather, you should use primitives such as LATCH, or components such as lpm_latch, which can be used in gdf or vhd files. We will use the design in Figure 7.8 only to illustrate the function of a NAND latch and to generate some timing data with the MAX PLUS II simulator.

In order to make MAX PLUS II synthesize this circuit as we have drawn it in Figure 7.8, we must select Global Project Logic Synthesis from the Assign Menu (Figure 7.9).

282 C H A P T E R 7 • Introduction to Sequential Logic

When we run the MAX PLUS II Timing Analyzer, we get the delay matrix shown in Figure 7.11. The delays are symmetrical for this circuit. The delay from nS to Q (7.5 ns) is through one gate; from nS to nQ (12.5 ns) is through two gates. These values are the same for the path from nR to nQ (7.5 ns; one gate) and from nR to Q (12.5 ns; two gates). We can see these changes on simulation waveforms for the SET and RESET functions.

FIGURE 7.12

RESET-to-SET transition

FIGURE 7.13

NAND Latch SET function simulation

The waveforms in Figure 7.13 also show this transition. The simulation window has a 2.5 ns grid, so three grid spaces are equivalent to 7.5 ns and five grid spaces to 12.5 ns. The waveforms show Q going HIGH 7.5 ns after nS goes LOW, followed by nQ going LOW at 12.5 ns after nS.

Figures 7.14 and 7.15 show the same thing for the RESET function. The latch is in a stable SET condition at time t 0 (Figure 7.14a). Input R goes LOW at t 0 (Figure 7.14b). At time t 7.5 ns, Q goes HIGH, which is transferred to the upper gate in the latch circuit Figure 7.14c). Since both inputs of the upper gate are now HIGH, Q goes LOW at time t 12.5 ns (Figure 7.14d). At this point the latch is stable in the RESET condition and the input R can return to the HIGH (inactive) state, as shown in Figure 7.14e. Figure 7.15 shows the simulation waveforms for this transition.

FIGURE 7.14

SET-to-RESET Transition

FIGURE 7.15

NAND latch RESET function simulation

WYSIWYG synthesis, resulting in unequal delays from the inputs to the Q output, which can lead to instability.

Latch as a Switch Debouncer

Pushbutton or toggle switches are sometimes used to generate pulses for digital circuit inputs, as illustrated in Figure 7.23. However, when a switch is operated and contact is made on a new terminal, the contact, being mechanical, will bounce a few times before settling into the new position. Figure 7.23d shows the effect of contact bounce on the waveform for a pushbutton switch. The contact bounce is shown only on the terminal where contact is being made, not broken.

FIGURE 7.23

Switches as Pulse Generators

Contact bounce can be a serious problem, particularly when a switch is used as an input to a digital circuit that responds to individual pulses. If the circuit expects to receive one pulse, but gets several from a bouncy switch, it will behave unpredictably.

A latch can be used as a switch debouncer, as shown in Figure 7.24a. When the pushbutton is in the position shown, the latch is set, since S 0 and R 1. (Recall that the NAND latch inputs are active LOW.) When the pushbutton is pressed, the R contact

FIGURE 7.24

NAND Latch as a Switch

Debouncer

288 C H A P T E R 7 • Introduction to Sequential Logic

bounces a few times, as shown in Figure 7.24b. However, on the first bounce, the latch is reset. Any further bounces are ignored, since the resulting input state is either S R 1 (no change) or S 1, R 0 (reset).

SOLUTION Figure 7.26 shows the timing diagrams of the two NOR latch circuits. In the circuit in Figure 7.25a, contact bounce causes the latch to oscillate in and out of the forbidden state of the latch (S R 1). This causes one of the two outputs to bounce for each contact closure. (Use the function table of the NOR latch to examine each part of the timing diagram to see that this is so.)

By making the resistors pull down rather than pull up, as in Figure 7.25b, the latch oscillates in and out of the no change state (S R 0) as a result of contact bounce. The first

FIGURE 7.26

Example 7.3

NOR Latch Circuits

bounce on the SET terminal sets the latch, and other oscillations are disregarded. The first bounce on the RESET input resets the latch, and further pulses on this input are ignored.

The principle illustrated here is that a closed switch must present the active input level to the latch, since switch bounce is only a problem on contact closure. Thus, a closed switch must make the input of a NOR latch HIGH or the input of a NAND latch LOW to debounce the switch waveform.

N O T E

The NOR latch is seldom used in practice as a switch debouncer. The pull-down resistors need to be about 500 or less to guarantee a logic LOW at the input of a TTL NOR gate. In such a case, a constant current of about 10 mA flows through the resistor connected to the normally closed portion of the switch. This value is unacceptably high in most circuits, as it draws too much idle current from the power supply. For this reason, the NAND latch, which uses higher-value pull-up resistors (about 1 k or larger) and therefore draws less idle current, is preferred for a switch debouncer.

SECTION 7.2 REVIEW PROBLEM

7.2Why is the input state S R 1 considered forbidden in the NOR latch? Why is the same state in the NAND latch the no change condition?

7.3Gated Latches

K E Y T E R M S

Gated SR latch An SR latch whose ability to change states is controlled by an extra input called the ENABLE input.

Steering gates Logic gates, controlled by the ENABLE input of a gated latch, that

steer a SET or RESET pulse to the correct input of an SR latch circuit.

Transparent latch (gated D latch) A latch whose output follows its data input when its ENABLE input is active.

Gated SR Latch

It is not always desirable to allow a latch to change states at random times. The circuit shown in Figure 7.27, calleda gated SR latch, regulates the times when a latch is allowed to change state.

The gated SR latch has two distinct subcircuits. One pair of gates is connected as an SR latch. A second pair, called the steering gates, can be enabled or inhibited by a control signal, called ENABLE, allowing one or the other of these gates to pass a SET or RESET signal to the latch gates.

The ENABLE input can be used in two principal ways: (1) as an ON/OFF signal, and

(2) as a synchronizing signal.

Figure 7.27b shows the ENABLE input functioning as an ON/OFF signal. When ENABLE 1, the circuit acts as an active-HIGH latch. The upper gate converts a HIGH at S to a LOW at S, setting the latch. The lower gate converts a HIGH at R to a LOW at R, thus resetting the latch.

When ENABLE 0, the steering gates are inhibited and do not allow SET or RESET signals to reach the latch gate inputs. In this condition, the latch outputs cannot change.