Digital design with CPLD applications and VHDL (R. Dueck, 2000)

300 C H A P T E R 7 • Introduction to Sequential Logic

Figure 7.40 shows a circuit that acts as a simplified positive edge detector. Edge detection depends on the fact that a gate output does not switch immediately when its input switches. There is a delay of about 3 to 10 ns from input change to output change, called propagation delay.

FIGURE 7.40

Positive Edge Detector

When input x, shown in the timing diagram of Figure 7.40, goes from LOW to HIGH, the inverter output, x, goes from HIGH to LOW after a short delay. This delay causes both x and x to be HIGH for a short time, producing a high-going pulse at the circuit output immediately following the positive edge at x.

When x returns to LOW, x goes HIGH after a delay. However, there is no time in this sequence when both AND inputs are HIGH. Therefore, the circuit output stays LOW after the negative edge of the input waveform.

Figure 7.41 shows how the D flip-flop circuit operates. When D 0 and the edge detector senses a positive edge at the CLK input, the output of the lower NAND gate steers a low-going pulse to the RESET input of the latch, thus storing a 0 at Q. When D 1, the upper NAND gate is enabled. The edge detector sends a high-going pulse to the upper steering gate, which transmits a low-going SET pulse to the output latch. This action stores a 1 at Q.

FIGURE 7.41

Operation of a D Flip-Flop

DFF

FIGURE 7.42

D Latch and D Flip-Flop

SOLUTION The simulation, shown in Figure 7.43, has a 200 ns grid. Several points on the waveform indicate the similarities and differences between the latch and flip-flop operation.

FIGURE 7.43

Simulation showing the Difference between D Latch and D Flip Flop

latch_ff.gdf latch_ff.scf

2.D goes LOW at 2 s. Both Q outputs go LOW at 2.8 s since the positive edge of the CLK and its HIGH level occur at the same time.

3.The D input goes HIGH at 4.4 s, in the middle of a CLK pulse. Since the CLK line is HIGH, Q_ latch changes immediately. Q_ flip_ flop does not change until the next positive edge, at 6 s.

4.D goes LOW at 7.8 s. Q_latch also changes at this time, since CLK is HIGH. Q_ flip_ flop changes on the next positive edge, at 9.2 s.

302 C H A P T E R 7 • Introduction to Sequential Logic

SOLUTION Figure 7.44b shows the output waveforms. Q0 follows D0 at each point where the clock input has a positive edge. One result of this is that the HIGH pulse on D0 between clock pulses 5 and 6 is ignored, since D0 0 on positive edges 5 and 6.

Since D1 Q0 and Q1 follows D1, the waveform at Q1 is the same as at Q0, but delayed by one clock cycle. If Q0 changes due to CLK, we assume that the value of D1 is the same as Q0 just before the clock pulse. This is because delays within the circuitry of the flip-flops ensure that their outputs will not change for several nanoseconds after an applied clock pulse. Therefore, the level at D1 remains constant long enough for it to be clocked into the second flip-flop.

The data entering the circuit at D0 are moved, or shifted, from one flip-flop to the next. This type of data movement, called “serial shifting,” is frequently used in data communi-

SECTION 7.4 REVIEW PROBLEM

7.4Which part of a D flip-flop accounts for the difference in operation between a D flipflop and a D latch? How does it work?

304 C H A P T E R 7 • Introduction to Sequential Logic

Figure 7.53 shows the circuit of a 3-bit synchronous counter. Unlike the circuit in Figure 7.49, the flip-flops in this circuit are clocked from a common source. Therefore, flip-flop delays do not add up through the circuit, and all the outputs change at the same time. Figure 7.54 shows a simulation of the circuit of Figure 7.53. Note that the outputs progress in a binary sequence, and there are no intermediate states.

FIGURE 7.54

Simulation of a 3-bit Synchronous Counter

The circuit works as follows:

1.Flip-flop 0 is configured for toggle mode (J0K0 11). Since the flip-flops in Figure 7.53 are positive edge-triggered, Q0 toggles on each positive clock edge.

2.Q0 is connected to inputs J1 and K1. Since these inputs are tied together, only two states are possible: no change (JK 00) or toggle (JK 11). If Q0 1, Q1 toggles. Otherwise, it does not change. This results in a Q1 waveform that toggles at half the rate of Q0.

3.J2 and K2 are both tied to the output of an AND gate. The AND gate output is HIGH if both Q1 and Q0 are HIGH. This makes Q2 toggle, since J2K2 11. In all other cases, there is no change on Q2. The result of this is that Q2 toggles every fourth clock pulse, the only times when Q1 and Q0 are both HIGH.

Asynchronous Inputs (Preset and Clear)

K E Y T E R M S

Synchronous inputs The inputs of a flip-flop that do not affect the flip-flop’s Q outputs unless a clock pulse is applied. Examples include D, J, and K inputs.

Asynchronous inputs The inputs of a flip-flop that change the flip-flop’s Q outputs immediately, without waiting for a pulse at the CLK input. Examples include preset and clear inputs.

Preset An asynchronous set function.

Clear An asynchronous reset function.

The D, J, and K inputs of the flip-flops examined so far are called synchronous inputs. This is because any effect they have on the flip-flop outputs is synchronized to the CLK input.

Another class of input is also provided on many flip-flops. These inputs, called asynchronous inputs, do not need to wait for a clock pulse to make a change at the output. The two functions usually provided are preset, an asynchronous set function, and clear, an

asynchronous reset function. These functions are generally active LOW, and are abbreviated PRE and CLR.

Figure 7.55 shows a modification to the JK flip-flop of Figure 7.46. The PRE and CLR inputs have direct access to the latch gates of the flip-flop and thus are not affected by the

308 C H A P T E R 7 • Introduction to Sequential Logic

FIGURE 7.55

PRE and CLR Inputs

FIGURE 7.56

Example 7.10

Waveforms

SOLUTION The Q waveform is shown in Figure 7.56. The asynchronous inputs cause an immediate change in Q, whereas the synchronous inputs must wait for the next negative clock edge. If asynchronous and synchronous inputs are simultaneously active, the asynchronous inputs have priority. This occurs in two places: pulse 3 (K, PRE) and pulse 10

(J, CLR).

The diagram shows the synchronous functions (no change, reset, set, and toggle) at each clock pulse and the asynchronous functions (preset and clear) at the corresponding transi-

tion points.

The function table of a negative edge-triggered JK flip-flop with preset and clear functions is shown in Table 7.9.