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Digital design with CPLD applications and VHDL (R. Dueck, 2000)

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260	C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits

FIGURE 6.23

BCD Adder (11⁄2 Digit Output)

4-bit Adder

Figure 6.23 shows how we can add two BCD digits and get a corrected output. The BCD adder circuit consists of a standard 4-bit parallel adder to get the binary sum and a code converter to translate it into BCD.

The Binary-to-BCD code converter operates on the binary inputs as follows:

1.A carry output is generated if the binary sum is in the range 01010 sum 10011 (BCD equivalent: 1 0000 sum 1 1001).

2.If the binary sum is less than 01001, the output is the same as the input.

3.If the sum is in the range 01010 sum 10011, the four LSBs of the input must be corrected to a BCD value. This can be done by adding 0110 to the four LSBs of the in-

put and discarding any resulting carry. We add 01102 (610) because we must account for six unused codes.

Let’s look at how each of these requirements can be implemented by a digital circuit.

Carry Output

The carry output will be automatically 0 for any uncorrected sum from 00000 to 01001 and automatically 1 for any sum from 10000 to 10011. Thus, if the binary adder’s carry output, which we will call C4 , is 1, the BCD adder’s carry output, C4, will also be 1.

Any sum falling between these ranges, that is, between 01010 and 01111, must have its MSB modiﬁed. This modifying condition is a function, designated C4 , of the binary adder’s sum outputs when its carry output is 0. This function can be simpliﬁed by a Karnaugh map, as shown in Figure 6.24, resulting in the following Boolean expression.

C4 4 3 4 2

The BCD carry output C4 is given by:

C4 C4 C4

C4 4 3 4 2

The BCD carry circuit is shown in Figure 6.25.

6.7 • BCD Adders

261

FIGURE 6.24

FIGURE 6.25

Carry as a Function of Sum

BCD Carry Circuit

Bits When C4 0

Sum Correction

The four LSBs of the binary adder output need to be corrected if the sum is 01010 or greater and need not be corrected if the binary sum is 01001 or less. This condition is indicated by the BCD carry. Let us designate the binary sum outputs as 4 3 2 1 and the BCD sum outputs as 4 3 2 1.

If C4 0, 4 3 2 1 4 3 2 1 0000;

If C4 1, 4 3 2 1 4 3 2 1 0110.

Figure 6.26 shows a BCD adder, complete with a binary adder, BCD carry, and sum correction. A second parallel adder is used for sum correction. The B inputs are the uncorrected binary sum inputs. The A inputs are either 0000 or 0110, depending on the value of the BCD carry.

4-bit Adder

3 2 1












			A4	A3 A2		A1	B4	B3 B2 B1
		Code	C4			4-bit Adder			C0
		Code	C4			4-bit Adder			C0
	converter				4	3	2	1
	converter				4	3	2	1



C4					4	3	2	1

FIGURE 6.26

BCD Adder

262	C H A P T E R	6 • Digital Arithmetic and Arithmetic Circuits

EXAMPLE 6.25		Write a VHDL ﬁle for a BCD adder, using two parallel adder components, such as in the
		logic diagram in Figure 6.26.

SOLUTION

bcd_add.vhd

PORT (
c0	: IN	BIT;
a, b	: IN	BIT_VECTOR (4 downto 1);
c4	: OUT	BIT;
sum	: OUT	BIT_VECTOR (4 downto 1));
END bcd_add;

ARCHITECTURE adder OF bcd add IS

—— Component declaration

COMPONENT add4par
PORT (
c0	: IN	BIT;
a, b	: IN	BIT_VECTOR (4 downto 1);
c4	: OUT	BIT;
sum	: OUT	BIT_VECTOR (4 downto 1));

END COMPONENT;

SIGNAL c4_bin : BIT;

SIGNAL sum_bin : BIT_VECTOR (4 downto 1);

SIGNAL a_bcd : BIT_VECTOR (4 downto 1);

SIGNAL b_bcd : BIT_VECTOR (4 downto 1);

SIGNAL c0_bcd: BIT;

BEGIN

—— Instantiate 4-bit adder (binary sum) add_bin: add4par

PORT MAP ( c0 c0,

aa,

bb,

c4 c4_bin, sum sum_bin);

——Instantiate 4-bit adder (binary-BCD converter) converter: add4par

PORT MAP ( c0 c0_bcd,


	a	a_bcd,
	b	b_bcd,
	sum sum);
——Connect components
c0_bcd	´0´;
b_bcd	sum_bin;
a_bcd(4)	´0´;
a_bcd(3)	c4		bin or (sum_bin(4) and sum_bin(3))
	or (sum_bin(4) and sum_bin(2));
a_bcd(2)	c4		bin or (sum_bin(4) and sum_bin(3))
	or (sum_bin(4) and sum_bin(2));
a_bcd(1)	´0´;
c4	c4_bin or (sum_bin(4) and sum_bin(3))
	or (sum_bin(4) and sum_bin(2));

END adder;

6.8 • Carry Generation in MAX PLUS II 263

Multiple-Digit BCD Adders

Several BCD adders can be cascaded to add multidigit BCD numbers. Figure 6.27 shows a 412 -digit BCD adder. The carry output of the most signiﬁcant digit is considered to be a half-digit since it can only be 0 or 1. The output range of the 412 -digit BCD adder is 00000 to 19999.

FIGURE 6.27

41⁄2-Digit BCD Adder

BCD adders are cascaded by connecting the code converter carry output of one stage to the binary adder carry input of the next most signiﬁcant stage. Each BCD output digit represents a decade, designated as the units, tens, hundreds, thousands, and ten thousands digits.

SECTION 6.7 REVIEW PROBLEM

6.11What is the maximum BCD sum of two 3-digit numbers with no carry input? How many digits are required to display this result on a numerical output?

6.8Carry Generation in MAX PLUS II

K E Y T E R M S

Speed grade A speciﬁcation that indicates the internal delay time that can be expected of a CPLD.

Expander buffer A MAX PLUS II primitive that supplies an inverted product term for general use within a CPLD.

The VHDL adder circuits implemented in Section 6.6 were all deﬁned using a ripple carry format. Is it necessary to design a fast carry circuit when compiling one of these adder designs in MAX PLUS II? Probably not.

Recall that the design strategy behind the fast carry circuit was to ﬂatten the gate network, that is, to replace a long network (many gates for the carry bit to pass through) with a wide one (fewer levels of gating). Also recall that any combinational logic function can be implemented as a sum-of-products (SOP) network, which inherently is a very ﬂat network form.

264	C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits

The internal circuit of a MAX7000S CPLD is a programmable SOP network. In order to program such a device, the MAX PLUS II compiler must analyze the design entity, break it into product terms and reassemble it as an SOP network. (This is an oversimpliﬁcation. Sometimes SOP outputs are fed back into the circuit to be reused by other parts of the circuit, thus lengthening the logic path.)

MAX PLUS II allows us to choose a style of logic synthesis that balances circuit speed and chip area occupied by the programmed circuit. The styles can be user-deﬁned or we can use one of three predeﬁned synthesis styles called Normal, Fast, and WYSIWYG (What You See Is What You Get). Each one of these styles is optimized for speed, area, or a compromise. The Normal and Fast styles disassemble the design entity and reassemble it after optimizing the logic according to the style rules. The WYSIWYG style allows us (rather than the compiler) to largely deﬁne the logic synthesis without altering our design format by very much.

To choose a synthesis style, select Global Project Logic Synthesis, from the MAX PLUS II Assign menu, as shown in Figure 6.28. A drop-down menu in the resulting dialog box, shown in Figure 6.29, allows us to select one of the three Altera-deﬁned synthesis styles.

FIGURE 6.28	FIGURE 6.29
Assigning a Synthesis Style (Assign Menu)	Assigning a Synthesis Style

N O T E

To use the WYSIWYG style, you must also check the box that says Multi-Level

Synthesis for MAX 5000/7000 Devices.

We can calculate the circuit delays for an adder by running the compiled design through the MAX PLUS II Timing Analyzer. Figure 6.30 shows an example of such an analysis for the parallel adder add4par.vhd with a Normal synthesis style and an EPM7128SLC84-7 as the selected device.

6.8 • Carry Generation in MAX PLUS II 265

FIGURE 6.30

Delay matrix for a 4-bit adder (Normal Synthesis)

The values in the Destination columns are the delays from logic level changes on the inputs speciﬁed by the Source rows. For example, a change on input a1 reaches the output sum1 in 7.5 ns and sum4 in 12.5 ns. Most of the entries in the c4 column have two values (7.5 ns and 11.5 ns), indicating that the delay to output carry is the same from all input bits (i.e., a fast carry). The actual delay to c4 will depend on the logic level change that takes place on the source line and thus which logic path is taken. The delay time of 7.5 ns is about the lowest value possible in the EPM7128SLC84-7 device. (The “ 7” tells us that the chip has a speed grade of minus 7, meaning an internal delay of about 7 ns.)

Figure 6.31 shows the timing analysis of the same adder with a WYSIWYG synthesis style. (The synthesis style is the only design change.) In this analysis, the delay from an input bit to c4 varies from 7.5 ns (from a4 or b4) to as much as 16.5 ns (for a1, b1, a2, or b2). Since the lower-order bits result in a longer delay to the carry bit, we can infer that the compiler has not synthesized a fast carry circuit.

FIGURE 6.31

Delay matrix for a 4-bit adder (WYSIWYG Synthesis)

266	C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits

We can examine the actual equations from the MAX PLUS II report ﬁle to conﬁrm our assessment. The synthesized equations for c4 are given below.

WYSIWYG Synthesis:

——Node name is ´c4´ ´|full_add:adder4| :12´

——Equation name is ´c4´, type is output

c4 LCELL( _EQ001 $ GND); _EQ001 a3 & b3 & b4

#b4 & _LC113 & _LC114

#a3 & a4 & b3

#a4 & _LC113 & _LC114

#a4 & b4;

——Node name is ´|full_add:adder2|:12´

——Equation name is ´_LC113´, type is buried

_LC113	LCELL( _EQ008 $ GND);
_EQ008		a2	&	b2
	#	a2	&	c0	&	_X007
	#	b2	&	c0	&	_X007
	#	a1	&	b1	&	_X002;
_X007	EXP		(!a1 & !b1);
_X002	EXP		(!a2 & !b2);

——Node name is ´|full_add:adder3|:9´

——Equation name is ´_LC114´, type is buried _LC114 LCELL( b3 $ a3);

Normal synthesis:

——Node name is ´c4´

——Equation name is ´c4´, location is LC123, type is output. c4 LCELL ( EQ001 $ VCC);

_EQ001 !a1 & _X001 & _X002					& _X003 & _X004
#	!b1 & !c0	&	_X001	&	_X003	& _X004
#	!a2 & !b2	&	_X003	&	_X004

#!a3 & !b3 & _X004

#!a4 & !b4;

_X001 EXP ( a2 & b2); _X002 EXP ( b1 & c0); _X003 EXP ( a3 & b3); _X004 EXP ( a4 & b4);

The function EXP(signal) is for a MAX PLUS II primitive called an expander buffer, which represents a shared logic expander in the CPLD. There will be more detail about this type of buffer in Chapter 8, but for now, just be aware that this type of buffer supplies inverted product terms for general use within the CPLD.

The Normal synthesis mode generates a sum-of-products equation that uses a number of expanders, but only one logic cell (i.e., one SOP output), indicated as LC123. The WYSIWYG synthesis uses an unnumbered output logic cell, which in turn uses two other logic cell outputs (LC113 and LC114) as inputs. Thus, in the Normal synthesis mode, the input signals propagate through one logic cell, and in the WYSIWYG mode, the input signals go through two layers of logic cells, increasing the path length, and thus the delay.

What can we conclude? If MAX PLUS II is allowed to synthesize a design for a full adder in the deﬁned Normal style, it will optimize the design equations to produce as ﬂat a network as possible. Thus we do not need to explicitly design an adder circuit to have a fast carry function.

Summary 267

S U M M A R Y

1.Addition combines an addend (x) and an augend (y) to get a sum (z x y).

2.Binary addition is based on four sums:

0 0 0

0 1 1

1 1 10

1 1 1 11

3.A sum of two bits generates a sum bit and a carry bit. (For the ﬁrst two sums above, the carry bit is 0; the last two sums have a carry of 1. The last sum includes a carry from a lowerorder bit.)

4.Subtraction combines a minuend (x) and a subtrahend (y) to get a difference (z x y).

5.Binary subtraction is based on the following four differences:

0 0 0

1 0 1

1 1 0

10 1 1

6.If the subtrahend bit is larger than the minuend bit, as in the fourth difference above, a 1 must be borrowed from the next higher-order bit.

7.Binary addition or subtraction can be unsigned, where the magnitudes of the operands and result are presumed to be positive, or signed, where the operands and result can be positive or negative. The sign is indicated by a sign bit.

8.The sign bit (usually MSB) of a binary number indicates that the number is positive if it is 0 and negative if it is 1.

9.Signed binary numbers can be written in true-magnitude, 1’s complement, or 2’s complement form. True magnitude has the same binary value for positive and negative numbers, with only the sign bit changed. A 1’s complement negative number is generated by inverting all bits of the positive number of the same magnitude. A 2’s complement negative number is generated by adding 1 to the equivalent 1’s complement number. Positive numbers are the same in all three forms.

10.1’s complement or 2’s complement binary numbers are used in signed addition or subtraction. Subtraction is performed by adding a negative number in complement form to another number in complement form (i.e., x y x ( y)). This technique does not work for true-magnitude form.

11.A negative sum or difference in 2’s complement subtraction must be converted to a positive form to read its magnitude (i.e., ( x) x).

12.A signed binary number, x, with n bits has a valid range of2n x ( 2n 1).

13.A negative number with a power-of-2 magnitude (i.e.,2n) is written in 2’s complement form as n 0s preceded by all 1s to ﬁll the deﬁned size of the number (e.g., in 8- bit 2’s complement form, 128 10000000 (1 followed

by seven 0s; 128 27); in 8-bit 2’s complement form, 8 11111000 (all 1s, followed by three 0s; 8 23).

14.If a sum or difference falls outside the permissible range of magnitudes for a 2’s complement number, it generates an overﬂow into the sign bit of the number. The result is that the sum of two positive numbers appears to be negative (e.g., 01111111 00000010 10000001; 127 2

129)or the sum of two negative numbers appears to be positive (e.g., 11111111 10000000 01111111, where the carry beyond the 8th place is discarded: 1 ( 128)129).

15.When adding two hexadecimal digits, any digit sum greater than 15 (F) can be converted to a hexadecimal value by subtracting 16 and carrying a 1 to the next digit position.

16.Hexadecimal numbers can be subtracted conventionally or by a complement method. To get the 16’s complement of a number, obtain the 15’s complement by subtracting the number from all Fs and adding 1 to the result.

17.Binary numbers can be used in nonpositional codes to represent numbers or alphanumeric characters.

18.Binary coded decimal (BCD) codes represent decimal numbers as a series of 4-bit groups of numbers. Natural BCD or 8421 code does this as a positionally weighted code for each digit (e.g., 158 0001 0101 1000 (NBCD)). Other codes, such as Excess-3, are not positionally weighted.

19.Gray code is a binary code that has a difference of one bit between adjacent codes. It can be generated by a set of XOR functions or by recognizing the symmetry inherent in the code. In any Gray code sequence, the MSB is 0 for the ﬁrst half of the sequence and 1 for the second half. The remaining bits are symmetrical about the halfway point of the sequence.

20.ASCII code represents alphanumeric characters and computer control codes as a 7-bit group of binary numbers. Alpha characters are listed in uppercase in columns 4 and 5 of the ASCII table. Lowercase alpha characters are in columns 6 and 7. Numeric characters are in column 3.

21.A half adder combines two bits to generate a sum and a carry. It can be represented by the following truth table:

A	B	COUT
0	0	0	0
0	1	0	1
1	0	0	1
1	1	1	0
1	1	1	0

22. From the half adder truth table, we can derive two equations:

COUT AB

A B

23.A full adder can accept an input carry from a lower-order adder and combine the input carry with two operands to generate

268	C H A P T E R 6 • Digital Arithmetic and Arithemtic Circuits

a sum and output carry. Its operation can be summarized in the following truth table:

A	B	CIN	COUT
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1
1	1	1	1	1

24.The following Boolean equations for a full adder can be derived from the truth table and Boolean algebra:

COUT (A B) CIN AB

(A B) CIN

25.Two half adders can be combined to make a full adder. Operands A and B go to the ﬁrst half adder. The sum output of the ﬁrst half adder and the carry input go to the inputs of the second half adder. The carry outputs of both half adders are combined in an OR gate.

26.Multiple full adders can be cascaded to make a parallel bi-

nary adder. Operands A1 and B1 are applied to the ﬁrst full adder. Carry bit C0 is grounded. A2 and B2 go to the second adder stage, and so on. The carry output of one stage is cascaded to the carry input of the following stage. This connection is called ripple carry.

27.Ripple carry has the disadvantage of increasing the time required to generate an output result as more stages are added. Fast carry, or look-ahead carry, examines all adder inputs simultaneously and generates each internal and output carry with a separate circuit. This makes the carry circuit wider, but ﬂatter, thus reducing the delay time of the circuit.

28.A parallel adder can be implemented in VHDL by creating a design entity for a full adder, then using multiple instances of the full adder as components in the parallel adder.

29.To use a component in a VHDL design hierarchy, we require a design entity that deﬁnes the component, a component declaration in the design entity that uses the component, and a component instantiation statement for every instance of the component in the higher-level design entity.

30.The general form of a design entity using components is:

ENTITY entity_name IS

PORT ( input and output deﬁnitions); END entity_name;

ARCHITECTURE arch_name OF entity_name IS component declaration (s);

signal declaration(s); BEGIN

Component instantiation(s); Other statements;

END arch_name;

31.The port map of a component maps the port names deﬁned in a component to the port, signal, or variable names deﬁned in the design entity that uses the component.

32.If all ports of a component are to be used in the same order as in the component deﬁnition in the original component design entity, the port map can simply contain the user names in the same order. For example:

adder1: full_add PORT MAP (a(1), b(1), c0, c(1), sum(1));

33.If only a portion of the component ports are to be used or they are not used in the same sequence as they are declared, the port map must be more explicit. For example:

adder1: full_add
PORT MAP ( b	b(1),
a	a(1),
c_in	c0,
sum	sum(1)),
c_out	c(1);

34.A GENERATE statement can be used to instantiate multiple instances of a component. The GENERATE statement has the form:

label:

FOR index IN range GENERATE statements;

END GENERATE;

35.MAX PLUS II will synthesize an adder to minimize carry delays without much intervention.

36.A parallel binary adder can be made into a 2’s complement subtractor by inverting one set of inputs and tying the input carry to a logic HIGH.

37.A parallel binary adder can be made into a 2’s complement adder/subtractor by using a set of XOR gates as programmable inverters and connecting the XOR control line to the carry input of the adder.

38.One method of detecting a sign bit overﬂow in a 2’s complement adder/subtractor is to compare the sign bits of the operands to the sign bit of the result. If the sign bits of the operands are the same as each other, but different

from the sign bit of the result, there has been an overﬂow.

The Boolean equation for this detector is given by V S

SA SB S SA SB.

39.Another method of overﬂow detection compares the carry out of the MSB of the adder/subtractor to the carry into the MSB. An overﬂow occurs if there is a carry out of or into the MSB, but not both. The Boolean equation for this detector is given by V Cn Cn 1, for an n-bit adder/subtractor.

40.A BCD adder adds two binary coded decimal (BCD) digits and generates a BCD digit and a carry bit.

41.Since BCD is a 4-bit code, BCD addition can be done with a 4-bit binary adder and a code converter. The code converter can be synthesized from another 4-bit binary adder and a circuit to generate a carry.

Glossary 269

G L O S S A R Y

1’s complement A form of signed binary notation in which negative numbers are created by complementing all bits of a number, including the sign bit.

10’s complement A way of writing decimal numbers where a negative number is generated by adding 1 to its 9’s complement.

2’s complement A form of signed binary notation in which negative numbers are created by adding 1 to the 1’s complement form of the number.

8421 Code (or NBCD; natural binary coded decimal) A BCD code that represents each digit of a decimal number by its 4-bit true binary value.

9’s complement A way of writing decimal numbers where a number is made negative by subtracting each of its digits from 9 (e.g., 726 999 726 273 in 9’s complement).

Addend The number in an addition operation that is added to another.

Alphanumeric code A code used to represent letters of the alphabet and numerical characters.

ASCII American Standard Code for Information Interchange. A 7-bit code for representing alphanumeric and control characters.

Augend The number in an addition operation to which another number is added.

BCD Binary coded decimal. A code that represents each digit of a decimal number by a 4-bit binary value.

BCD adder A parallel adder whose output is in groups of 4 bits, each group representing a BCD digit.

Borrow A digit brought back from a more signiﬁcant position when the subtrahend digit is larger than the minuend digit.

Carry A digit which is “carried over” to the next most signiﬁcant position when the sum of two single digits is too large to be expressed as a single digit.

Carry bit A bit that holds the value of a carry (0 or 1) resulting from the sum of two binary numbers.

Cascade To connect an output of one device to a input of another, often for the purpose of expanding the number of bits available for a particular function.

Case shift Changing letters from capitals (UPPERCASE) to small letters (lowercase) or vice versa.

Component A complete VHDL design entity that can be used as a part of a higher-level ﬁle in a hierarchical design.

Component declaration statement A statement that deﬁnes the input and output port names of a component used in a VHDL design entity.

Component instantiation statement A statement that maps port names of a VHDL component to the port names, internal signals, or variables of a higher-level VHDL design entity.

Difference The result of a subtraction operation.

End-around carry An operation in 1’s complement subtraction where the carry bit resulting from a sum of two 1’s complement numbers is added to that sum.

Excess-3 code A BCD code that represents each digit of a decimal number by a binary number derived by adding 3 to its 4-bit true binary value. Excess-3 code has the advantage of being “self-complementing.”

Expander buffer A MAX PLUS II primitive that supplies an inverted product term for general use within a CPLD.

Fast carry (or look-ahead carry) A gate network which generates a carry bit directly from all incoming operand bits, independent of the operation of each full adder stage.

Full adder A circuit that will add a carry bit from another full or half adder and two operand bits to produce a sum bit and a carry bit.

GENERATE statement A VHDL construct that is used to create repetitive portions of hardware.

Gray code A binary code which progresses such that only one bit changes between two successive codes.

Half adder A circuit that will add two bits and produce a sum bit and a carry bit.

Hierarchy A group of design entities associated in a series of levels or layers in which complete designs form portions of another, more general design entity. The more general design is considered to be the higher level of the hierarchy.

Instantiate To use an instance of a component.

Magnitude bits The part of a signed binary number that tell us how large the number is (i.e., its magnitude).

Minuend The number in a subtraction operation from which another number is subtracted.

Operand A number upon which an arithmetic function operates (e.g., in the expression x y z, x and y are the operands).

Overﬂow An erroneous carry into the sign bit of a signed binary number which results from a sum larger than can be represented by the number of magnitude bits.

Parallel binary adder A circuit, consisting of n full adders, which will add two n-bit binary numbers. The output consists of n sum bits and a carry bit.

Port An input or output of a VHDL design entity or component.

Ripple carry A method of passing carry bits from one stage of a parallel adder to the next by connecting COUT of one full adder to CIN of the following stage.

Self-complementing A code that automatically generates a negative-equivalent (e.g., 9’s complement for a decimal code) when all its bits are inverted.

Sign bit A bit, usually the MSB, that indicates whether a signed binary number is positive or negative.

Signed binary arithmetic Arithmetic operations performed using signed binary numbers.

Signed binary number A binary number of ﬁxed length whose sign is represented by one bit, usually the most signiﬁcant bit, and whose magnitude is represented by the remaining bits.

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