Digital design with CPLD applications and VHDL (R. Dueck, 2000)

172 C H A P T E R 5 • Combinational Logic Functions

FIGURE 5.23

Convention for Displaying Decimal Digits

display digit 1 by illuminating segments b and c, although segments e and f would also work.

The electrical requirements for an LED circuit are simple. Since an LED is a diode, it conducts when its anode is positive with respect to its cathode, as shown in Figure 5.24a. A decoder/driver for an LED display will illuminate an element by completing this circuit, either by supplying VCC or ground. A series resistor limits the current to prevent the diode from burning out and to regulate its brightness. If the anode is 5 volts with respect to cathode, the resistor value should be in the range of 220 to 470 .

FIGURE 5.24

Electrical Requirements for LED Displays

Seven-segment displays are configured as common anode or common cathode, as shown in Figures 5.24b and c. In a common cathode display, the cathodes of all LEDs are connected together and brought out to one or more pin connections on the display package. The cathode pins are wired externally to the circuit ground. We illuminate the segments by applying logic HIGHs to individual anodes.

Similarly, the common anode display has the anodes of the segments brought out to one or more common pins. These pins must be tied to the circuit power supply (VCC). The segments illuminate when a decoder/driver makes their individual cathodes LOW. Figure 5.25 shows how the diodes could be physically laid out in a common anode display.

The two types of displays allow the use of either active HIGH or active LOW circuits to drive the LEDs, thus giving the designer some flexibility. However, it should be noted that the majority of seven-segment decoders are for common-anode displays.

174 C H A P T E R 5 • Combinational Logic Functions

table for each of the outputs, showing which must be active for every digit we wish to display. The truth table for a common-anode decoder (active LOW outputs) is given in Table 5.3.

Table 5.3 Truth Table for Common Anode BCD-to-Seven-Segment Decoder

The illumination of each segment is determined by a Boolean function of the input variables, D3D2D1D0. From the truth table, the function for segment a is

a D3D2D1D0 D3D2D1D0 D3D2D1D0

(Since the display is active-LOW, this means segment a is OFF for digits 1, 4, and 6.)

If we assume that inputs 1010 to 1111 are never going to be used (“don’t care states”, symbolized by X), we can make any of these states produce HIGH or LOW outputs, depending on which is most convenient for simplifying the segment functions. Figure 5.27a shows a Karnaugh map simplification for segment a. The resultant function is

a D3D2D1D0 D2D0

The corresponding partial decoder is shown in Figure 5.27b.

We could do a similar analysis for each of the other segments, but if we are programming the decoder function into a CPLD, it is just as simple to write the truth table directly into a selected signal assignment statement, as shown in the VHDL code that follows.

——bcd_7seg.vhd

——BCD-to-seven-segment decoder

bcd_7seg.vhd

SIGNAL input : BIT_VECTOR (3 downto 0); SIGNAL output: BIT_VECTOR (6 DOWNTO 0); BEGIN

input <= d3 & d2 & d1 & d0; WITH input SELECT

output <= “0000001” WHEN “0000”, “1001111” WHEN “0001”,

176 C H A P T E R 5 • Combinational Logic Functions

Why not simply define d as a vector? If we wish to create a graphic symbol for the seven-segment decoder, the above method creates a symbol shown with four separate inputs, rather than a single thick line for a 4-bit bus input. The design will work either way.

For each value of input, a signal assignment defines the output vector, each bit of which represents the value of one segment. For example, the first clause (“0000001” WHEN “0000”) sets all segments ON except segment g, thus displaying the digit “0”.

As a variation, we could define a signal called d_inputs of type INTEGER with RANGE 0 to 9. The WHEN clauses would evaluate the integer values 0 to 9, as follows.

WITH d_inputs SELECT

output <= “0000001” WHEN 0, “1001111” WHEN 1, “0010010” WHEN 2, “0000110” WHEN 3,

“1001100” WHEN 4, “0100100” WHEN 5, “0100000” WHEN 6, “0001111” WHEN 7,

“0000000” WHEN 8,

“0000100” WHEN 9,

“1111111” WHEN others; —— blank

Ripple Blanking

K E Y T E R M S

Ripple blanking A technique used in a multiple-digit numerical display that suppresses leading or trailing zeros in the display, but allows internal zeros to be displayed.

RBI Ripple blanking input

RBO Ripple blanking output

PROCESS A VHDL construct that contains statements that are executed if there is a change in a signal in its sensitivity list.

Sensitivity list A list of signals in a PROCESS statement that are monitored to determine whether the PROCESS should be executed.

CASE statement A VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable.

IF statement A VHDL construct within a process that executes a series of statements, if a Boolean test condition is true.

A feature often included in seven-segment decoders is ripple blanking. The ripple blanking feature allows for suppression of leading or trailing zeros in a multiple digit display, while allowing zeros to be displayed in the middle of a number.

Each display decoder has a ripple blanking input (RBI) and a ripple blanking output (RBO), which are connected in cascade, as shown in Figure 5.28. If the decoder input D3D2D1D0 is 0000, it displays digit 0 if RBI 1 and shows a blank if RBI 0.

If RBI 1 OR D3D2D1D0 is (NOT 0000), then RBO 1. When we cascade two or more displays, these conditions suppress leading or trailing zeros (but not both) and still display internal zeros.

To suppress leading zeros in a display, ground the RBI of the most significant digit decoder and connect the RBO of each decoder to the RBI of the next least significant digit. Any zeros preceding the first nonzero digit (9 in this case) will be blanked, as RBI 0 AND D3D2D1D0 0000 for each of these decoders. The 0 inside the number 904 is displayed since its RBI 1.

178C H A P T E R 5 • Combinational Logic Functions

——CASE statement within a PROCESS

PROCESS (__signal_name, __signal_name, __signal_name)

BEGIN

CASE __expression IS

WHEN __constant_value => __statement; __statement;

WHEN __constant_value => __statement; __statement;

WHEN OTHERS => __statement; __statement;

END CASE;

END PROCESS;

Whether the digit “0” is displayed or suppressed is conditional upon the value of RBI. This can be tested by an IF statement within the PROCESS. An IF statement executes one or more VHDL statements, depending on the state of a test condition. It has the following syntax.

IF __expression THEN __statement; __statement;

ELSIF __expression THEN

__statement; __statement;

ELSE

__statement; __statement;

END IF;

The following VHDL code demonstrates the ripple blanking function.

–– sevsegrb.vhd

a, b, c, d, e, f, g, nRBO : OUT BIT); END sevsegrb;

ARCHITECTURE seven_segment OF sevsegrb IS

SIGNAL input: BIT_VECTOR (3 DOWNTO 0);

SIGNAL output: BIT_VECTOR (6 DOWNTO 0);

BEGIN

input <= d3 & d2 & d1 & d0; —— Process Statement PROCESS (input, nRBI)

BEGIN

IF (input = “0000” and nRBI =‘0’) THEN

— — 0 suppressed

ELSIF (input = “0000” and nRBI = ‘1’) THEN

— — 0 displayed

ELSE

CASE input IS

WHEN “0001” => output <= “1001111”; —— 1

END PROCESS;

END seven_segment;

SECTION 5.1C REVIEW PROBLEM

5.3When would it be logical to suppress trailing zeros in a multiple-digit display and when should trailing zeros be displayed?

5.2Encoders

K E Y T E R M S

Encoder A circuit that generates a binary code at its outputs in response to one or more active input lines.

Priority encoder An encoder that generates a binary or BCD output corresponding to the subscript of the active input having the highest priority. This is usually defined as the input with the largest subscript value.

The function of a digital encoder is complementary to that of a digital decoder. A decoder activates a specified output for a unique digital input code. An encoder operates in the reverse direction, producing a particular digital code (e.g., a binary or BCD number) at its outputs when a specific input is activated.

Figure 5.29 shows an 3-bit binary encoder. The circuit generates a unique 3-bit binary output for every active input provided only one input is active at a time.

The encoder has only 8 permitted input states out of a possible 256. Table 5.4 shows the allowable input states, which yield the Boolean equations used to design the encoder. These Boolean equations are:

Q2 D7 D6 D5 D4

Q1 D7 D6 D3 D2

Q0 D7 D5 D3 D1

The D0 input is not connected to any of the encoding gates, since all outputs are in their LOW (inactive) state when the 000 code is selected.