Digital design with CPLD applications and VHDL (R. Dueck, 2000)

hi_pri8a.vhd

hi_pri8b.vhd hi_pri8b.scf

2.Examine each code. For a code with value n, add a Dn term to each Q equation where there is a 1. For example, for code 111, add the term D7 to the equations for Q2, Q1, and Q0. For code 110, add the term D6 to the equations for Q2 and Q1. (Steps 1 and 2 generate the nonpriority encoder equations listed earlier.)

3.Modify any Dn terms to ensure correct priority. Every time you write a Dn term, look at the previous lines in the table. For each previous code with a 0 in the same column as the 1 that generates Dn, use an AND function to combine Dn with a corresponding D. For example, code 101 generates a D5 term in the equations for Q2 and Q0. The term in the Q2 equation need not be modified because there are no previous codes with a 0 in

the same column. The term in the Q0 equation must be modified since there is a 0 in the Q0 column for code 110. This generates the term D6D5.

The equations from the 3-bit encoder of Figure 5.29 are modified by the priority encoding principle as follows:

Q2 D7 D6 D5 D4

Q1 D7 D6 D5D4D3 D5D4D2

Q0 D7 D6D5 D6D4D3 D6D4D2D1

VHDL Priority Encoder

The most obvious way to program a priority encoder inVHDL is to use the equations derived in the previous section in a set of concurrent signal assignment statements, as follows.

vhd

IS

PORT(

d : IN BIT_VECTOR(7 downto 0); q : OUT BIT_VECTOR (2 downto 0));

END hi_pri8a;

ARCHITECTURE a OF hi_pri8a IS

BEGIN

——Concurrent Signal Assignments

q(2) <= d(7) or d(6) or d(5) or d(4);

q(1) <= d(7) or d(6)

or ((not d(5)) and (not d(4)) and d(3)) or ((not d(5)) and (not d(4)) and d(2));

q(0) <= d(7) or ((not d(6)) and d(5))

or ((not d(6)) and (not d(4)) and d(3))

or ((not d(6)) and (not d(4)) and (not d(2)) and d(1));

END a;

Although this code works, it is not terribly elegant, nor does it give any insight into the operation of the encoder circuit. Also, if we expand our encoder output by one or more bits, the equations become more cumbersome with each new bit and soon become impractically large and susceptible to typing errors. A VHDL conditional signal assignment statement is an ideal alternative for use in a priority encoder circuit. A section of VHDL code using this format is shown below.

–— hi_pri8b.vhd ENTITY hi_pri8b IS PORT(

d : IN BIT_VECTOR (7 downto 0); q : OUT INTEGER RANGE 0 to 7);

END hi_pri8b;

HIPR/BCD

FIGURE 5.32

BCD Priority Encoder

Table 5.7 Truth Table of a BCD Priority Encoder

FIGURE 5.33

Simulation File for a BCD Priority Encoder

S0

S1

D0

D1

D2

D3

FIGURE 5.34

4-to-1 Multiplexer

5.4State the main limitation of the 3-bit binary encoder shown in Figure 5.29. How can the encoder be modified to overcome this limitation?

5.3Multiplexers

K E Y T E R M S

Multiplexer A circuit that directs one of several digital signals to a single output, depending on the states of several select inputs.

Data inputs The multiplexer inputs that feed a digital signal to the output when selected.

Select inputs The multiplexer inputs that select a digital input channel.

Double-subscript notation A naming convention where two or more numerically related groups of signals are named using two subscript numerals. Generally, the first digit refers to a group of signals and the second to an element of a group. (e.g., X03 represents element 3 of group 0 for a set of signal groups, X.)

A multiplexer (abbreviated MUX) is a device for switching one of several digital signals to an output, under the control of another set of binary inputs. The inputs to be switched are called the data inputs; those that determine which signal is directed to the output are called the select inputs.

For any given combination of S1S0, only one of the above four product terms will be enabled. For example, when S1S0 10, the equation evaluates to:

Y (D0 0) (D1 0) (D2 1) (D3 0) D2

The MUX equation can be described by a truth table as in Table 5.8. The subscript of the selected data input is the decimal equivalent of the binary combination S1S0.

Figure 5.35 shows two symbols used for a 4-to-1 multiplexer. The first symbol shows the data and select inputs as individual lines. The second symbol shows the data inputs as a single 4-bit bus line and the select inputs as a 2-bit bus.

mux4.vhd

mux4.scf

select inputs through an increasing binary sequence, we can see the different input waveforms appear at the output in a predictable sequence, as shown by the simulation waveforms in Figure 5.37. The frequencies shown in the simulation were chosen to make as great a contrast as possible between adjacent inputs so that the different selected inputs could easily be seen.

FIGURE 5.37

Simulation Waveforms for a 4-to-1 MUX

In Figure 5.37, we initially see the D0 waveform appearing at the Y output when S1S0 00, followed in sequence by the D1, D2, and D3 waveforms when S1S0 01, 10, and 11, respectively. (The S1S0 input combination is shown as a single hexadecimal value between 0 and 3, labelled S[1..0].)

This simulation can be created in the MAX PLUS II simulator by defining a base clock pulse length (e.g., 40 ns) and assigning that to one of the inputs (D1 in this case). Other input waveforms are set to periods of 2, 4, and 8 times the base waveform period (for D3, D2, and D0, respectively). The select input count waveforms are set to allow three cycles of the longest waveform (D0) to appear at Y when selected.

VHDL Implementation of Multiplexers

A multiplexer can be represented in MAX PLUS II as a Graphic Design File, similar to the diagram of Figure 5.34, or in a hardware description language such as VHDL.

Several different VHDL constructs can be used to define a multiplexer. We can use a concurrent signal assignment statement, a selected signal assignment statement, or a CASE statement within a PROCESS. We will briefly look at each form for a 4-to-1 multiplexer. Later, you will be required to extend these constructs to larger multiplexer circuits.

Concurrent Signal Assignment

Recall that the concurrent signal assignment statement takes the form:

__signal <= __expression;

We can use this to encode the Boolean expression that describes a 4-to-1 MUX. The VHDL file that incorporates this statement is as follows.

signals (d0 to d3) to output,

——depending on status of select bits (s1, s0).