Digital design with CPLD applications and VHDL (R. Dueck, 2000)

290 C H A P T E R 7 • Introduction to Sequential Logic

FIGURE 7.27

Gated SR Latch

Figure 7.27c shows the ENABLE input as a synchronizing signal. A periodic pulse waveform is present on the ENABLE line. The S and R inputs are free to change at random, but the latch outputs will change only when the ENABLE input is active. Since the ENABLE pulses are equally spaced in time, changes to the latch output can occur only at fixed intervals. The outputs can change out of synchronization if S or R change when ENABLE is HIGH. We can minimize this possibility by making the ENABLE pulses as short as possible.

Table 7.4 represents the function table for a gated SR latch.

Table 7.4 Gated SR Latch Function Table

Draw the output waveforms, Q1 and Q2. Describe how the length of the ENABLE pulse affects the output of each latch, assuming that the intent of each circuit is to synchronize the output changes to the beginning of the ENABLE pulse.

FIGURE 7.28

Example 7.4

Effect of ENABLE Pulse Width

SOLUTION Figure 7.28b shows the completed timing diagram. The longer ENABLE pulse at latch 1 allows the output to switch too soon during pulses 1 and 4. (“Too soon” means before the beginning of the next ENABLE pulse.) In each of these cases, the S and R inputs change while the ENABLE input is HIGH. This premature switching is eliminated in latch 2 because the S and R inputs change after the shorter ENABLE pulse is finished. A shorter pulse gives less chance for synchronization error, since the time for possible output

changes is minimized.

Transparent Latch (Gated D Latch)

Figure 7.29 shows the equivalent circuit of a gated D (“data”) latch, or transparent latch. This circuit has two modes. When the ENABLE input is HIGH, the latch is transparent because the output Q goes to the level of the data input, D. (We say, “Q follows D.”) When the ENABLE input is LOW, the latch stores the data that was present at D when ENABLE was last HIGH. In this way, the latch acts as a simple memory circuit.

292 C H A P T E R 7 • Introduction to Sequential Logic

FIGURE 7.29

Transparent Latch

The latch in Figure 7.29 is a modification of the gated SR latch, configured so that the S and R inputs are always opposite. Under these conditions, the states S R 0 (no change) and S R 1 (forbidden) can never occur. However, the equivalent of the no change state happens when the ENABLE input is LOW, when the latch steering gates are inhibited.

Figure 7.30 shows the operation of the transparent latch in the inhibit (no change), set, and reset states. When the latch is inhibited, the steering gates block any LOW pulses to the latch gates; the latch does not change states, regardless of the logic level at D.

FIGURE 7.30

Operation of Transparent Latch

If EN 1, Q follows D. When D 1, the upper steering gate transmits a LOW to the SET input of the latch and Q 1. When D 0, the lower steering gate transmits a LOW to the RESET input of the output latch and Q 0.

Table 7.5 shows the function table for a transparent latch.

294 C H A P T E R 7 • Introduction to Sequential Logic

Another method, recommended by the MAX PLUS II documentation, is to instantiate a LATCH primitive in a VHDL file. The primitive is contained in the altera library, in a package called maxplus2. The component declaration for this primitive is:

COMPONENT LATCH

END COMPONENT;

Since the component declaration is in the maxplus2 package, you do not have to declare it in the file in which you are using it. A VHDL file that uses the latch primitive is listed next. The component declaration uses STD LOGIC types, so we must include the type definitions in the ieee library (std_logic_1164 package).

lch_prim.vhd

USE ieee.std_logic_1164.ALL;

LIBRARY altera;

USE altera.maxplus2.ALL;

FIGURE 7.33

Example 7.5

Sensor Placement in a Traffic

Intersection

296 C H A P T E R 7 • Introduction to Sequential Logic

SOLUTION Figure 7.35 shows the completed timing diagram. The ENABLE input synchronizes the random sensor pattern to a 5-second standard interval. A HIGH on any Q output indicates a car over a sensor at the beginning of the interval. For example, at the beginning of the first interval, there is a car in the northbound lane (Q1) and one in the

southbound lane (Q2). Similar interpretations can be made for each interval.

Multi-bit Latches in VHDL

K E Y T E R M S

Library of Parameterized Modules (LPM) A standardized set of components for which certain properties can be specified when the component is instantiated.

Parameter (in an LPM component) A property of a component that can be specified when the component is instantiated.

Generic map A VHDL construct that maps one or more parameters of a component to a value for that instance of the component.

Port map A VHDL construct that maps the name of a port in a component to the name of a port, variable, or signal in a design entity that uses the component.

We can easily use VHDL to implement latches with multiple D inputs and Q outputs, but with a common ENABLE line, as in Figure 7.34. Three approaches are:

1.Use a behavioral description, as we did earlier for a single latch (d_lch.vhd). Use STD_LOGIC_VECTOR types for D and Q, rather than STD_LOGIC.

2.Altera recommends using a latch primitive or predefined component, rather than creating your own latch structures. We can use multiple LATCH primitives, instantiated by a GENERATE statement, as we did for multiple instances of a full adder in Chapter 6.

3.Use a latch component from the Library of Parameterized Modules (LPM). These components are specified in the lpm_components package in the lpm library.

Certain properties of an LPM component, such as the number of inputs or outputs, can be specified when the component is instantiated. These properties are referred to as parameters, and are listed in a generic map. For example, to make the latch output and input four bits wide, we set the parameter called LPM_WIDTH to a value of 4. The various parameters of an LPM component can be found in the LPM Quick Reference on the CD that accompanies this book or in the MAX PLUS II Help menu under

Megafunctions/LPM.

An input or output of an LPM component is called a port. A port map is used to make a correspondence between the port names in the component declaration and the port names used in the file containing the component. Since LPM components are declared in a separate package, we must refer to the MAX PLUS II Help or the LPM Quick Reference to determine the port names for a component. LPM components are instantiated the same as any other component.

The three VHDL files that follow each specify a 4-bit latch with common enable, each using one of the above methods.

Behavioral Description:

——ltch4bhv.vhd

——D latch with active-HIGH level-sensitive enable

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

298 C H A P T E R 7 • Introduction to Sequential Logic

ARCHITECTURE a OF ltch4lpm IS

BEGIN

—— Instantiate latch from an LPM component latch4: lpm_latch

GENERIC MAP (LPM_WIDTH 4) PORT MAP (data d_in,

gate enable, q

END a;

All three files can be tested with the same simulation, shown in Figure 7.36. The inputs, d_in, represent a 4-bit group of signals, as do the outputs, q_out. An increasing count, from 5 to C (0101 to 1100) is applied to d_in. This count contains both states (0 and 1) for each input bit. For each applied input state, the output bus, q_out, does not change until the enable line goes HIGH.

FIGURE 7.36

Simulation of a 4-bit D Latch

SECTION 7.3 REVIEW PROBLEM

7.3Write the VHDL code for a 16-bit latch with common active-HIGH enable, using MAX PLUS II latch primitives.

7.4Edge-Triggered D Flip-Flops

K E Y T E R M S

Edge The HIGH-to-LOW (negative edge) or LOW-to-HIGH (positive edge) transition of a pulse waveform.

CLOCK An enabling input to a sequential circuit that is sensitive to the positiveor negative-going edge of a waveform.

Edge-triggered Enabled by the positive or negative edge of a digital waveform.

Edge-sensitive Edge-triggered.

Level-sensitive Enabled by a logic HIGH or LOW level.

Flip-flop A sequential circuit based on a latch whose output changes when its

CLOCK input receives an edge.

In Example 7.4, we saw how a shorter pulse width at the ENABLE input of a gated latch increased the chance of the output being synchronized to the ENABLE pulse waveform. This is because a shorter ENABLE pulse gives less chance for the SET and RESET inputs to change during the time the latch is enabled.

A logical extension of this idea is to enable the latch for such a small time that the width of the ENABLE pulse is almost zero. The best approximation we can make to this is to allow changes to the circuit output only when an enabling, or CLOCK, input receives the edge of an input waveform. An edge is the part of a waveform that is in transition from