310 C H A P T E R 7 • Introduction to Sequential Logic
Figure 7.58 shows a set of simulation waveforms that illustrate the asynchronous clear function. When RESET is HIGH, the count proceeds normally. The positive clock edge at 440 ns drives the counter to state 011. The reset pulse at 460 ns sets the counter to 000 as soon as it goes LOW. On the next clock edge, the count proceeds from 000.
FIGURE 7.58
Simulation of Synchronous Counter with Asynchronous Reset
The function that sets all flip-flops in a circuit to a known initial state is sometimes called Master Reset.
SECTION 7.5 REVIEW PROBLEM
7.5What is the main difference between synchronous and asynchronous circuits, such as the two counters in Figures 7.49 and 7.53? What disadvantage is there to an asynchronous circuit?
7.6Edge-Triggered T Flip-Flops
K E Y T E R M
T (toggle) flip-flop A flip-flop whose output toggles between HIGH and LOW
states on each applied clock pulse when a synchronous input, called T, is active.
In the section on the JK flip-flop, we saw how that device can be set to toggle between HIGH and LOW output states. Other types of flip-flops can perform this function, as well. For example, Figure 7.59 shows a D flip-flop configured for toggle operation. Since Q follows D and D Q in this circuit, then the flip-flop output must change to its opposite state with each clock pulse. Figure 7.60 shows a MAX PLUS II simulation of this circuit.
notg2d.gdf |
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NOT |
PRN |
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CLRN |
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FIGURE 7.59
D Flip-Flop Configured for Toggle Function
7.6 • Edge-Triggered T Flip-Flops |
311 |
FIGURE 7.60
Simulation of D Flip-Flop in Toggle Mode
It is seldom useful for flip-flops in synchronous circuits to be permanently configured in toggle mode. What made the JK flip-flops suitable elements for the synchronous counter in Figure 7.53 was the fact that sometimes they toggled and sometimes they didn’t, depending on the current point in the output sequence of the counter. Figure 7.61 shows a D flip-flop configured for a switchable toggle function.
FIGURE 7.61 |
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Switchable Toggle Function for |
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a D Flip-Flop |
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d_toggle.gdf d_toggle.scf
The XOR gate acts as an inverter when the T input is HIGH and as a noninverting buffer when T is LOW. Thus, when T is LOW, the Q output is circulated back to the D input of the flip-flop and the current value of Q is reloaded on the next clock pulse. When T is HIGH, the circuit acts like that of Figure 7.59 and toggles.
A T flip-flop has this equivalent function. Figure 7.62 shows the symbol of a T flipflop in a MAX PLUS II Graphic Design File. A MAX PLUS II simulation in Figure 7.63 shows the operation of this device. The Q output toggles on each clock pulse when
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FIGURE 7.63
Simulation of T Flip-Flop
312 C H A P T E R 7 • Introduction to Sequential Logic
T is HIGH; otherwise Q retains its last value. A function table for the T flip-flop is shown in Table 7.10.
Table 7.10 Function Table for a T
Flip-Flop
CLK |
T |
Qt 1 |
Function |
↑ |
0 |
Qt |
No Change |
↑ |
1 |
Qt |
Toggle |
0 |
X |
Qt |
Inhibited |
1 |
X |
Qt |
Inhibited |
↓ |
X |
Qt |
Inhibited |
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SECTION 7.6 REVIEW PROBLEM
7.6Draw a circuit showing how the JK flip-flops in Figure 7.53 can be replaced by T flipflops.
7.7Timing Parameters
K E Y T E R M S
Setup time (tsu) The time required for the synchronous inputs of a flip-flop to be stable before a CLK pulse is applied.
Hold time (th) The time that the synchronous inputs of a flip-flop must remain stable after the active CLK transition is finished.
Pulse width (tw) Minimum time required for an active-level pulse applied to a CLK, CLR, or PRE input, as measured from the midpoint of the leading edge of the pulse to the midpoint of the trailing edge.
Recovery time (trec) Minimum time from the midpoint of the trailing edge of aCLR or PRE pulse to the midpoint of an active CLK edge.
Propagation delay The time required for the output of a digital circuit to change states after a change at one or more of its inputs.
Flip-flops are electrical devices with inherent internal switching delays. As such, they have specific requirements for the timing of the input and output waveforms in order for them to operate reliably. We will examine the basic timing requirements for two small scale integration (SSI) devices: the 74LS107A JK flip-flop (LSTTL family) and the 74HC107 JK flip-flop (high-speed CMOS family). Figure 7.64 shows some of the basic timing requirements of a JK flip-flop.
Figure 7.64a illustrates the definitions of setup time (tsu), hold time (th), and pulse width (tW). The notation used for the “J or K” waveform indicates that the J or K input could be at either logic level and makes a transition to the opposite level at some point. The setup time is measured from the midpoint of the J or K transition to the midpoint of the active CLK edge. The logic level on the J or K input must be steady for at least this time for the flip-flop to operate correctly. Setup time for both LSTTL and high-speed CMOS flipflops is about 20 ns.
Similarly, the hold time is measured from the midpoint of the CLK transition to the midpoint of the next J or K transition. The J or K level must be held steady for at least this time to ensure dependable operation. Hold time is 0 for LSTTL and 3 ns for a high-speed CMOS flip-flop.
The pulse width, tw, shows how long the CLK needs to be held LOW after an active CLK edge. Although the LOW level does not itself latch data into the flip-flop, internal logic levels must reach a steady state before the device can accept a new clock pulse. This
7.7 • Timing Parameters |
313 |
FIGURE 7.64
Timing Parameters of a JK Flip-Flop
minimum pulse width allows the necessary time for these internal transitions. The data sheet for a 74HC107 flip-flop (high-speed CMOS) gives the clock pulse width as 16 ns; a data sheet for a 74LS107A device gives the value as 20 ns.
Figure 7.64b shows the pulse width required at the CLR input, the propagation delay from CLR to Q and Q, and the recovery time that must be allowed from the end of a CLR pulse to the beginning of a CLK pulse. These times also apply to a pulse on the PRE input of a flip-flop.
Propagation delay is the result of internal electrical delays, primarily the charging and discharging of internal capacitances of the gate transistor junctions. The practical result of this is that a pulse at the CLR input makes Q go LOW, but not immediately; there is a delay of several nanoseconds between input pulse and output response.
Propagation delay is defined by the direction of the output transition. The delay at Q, which goes from HIGH to LOW, is called tpHL. The delay at Q, which goes from LOW to HIGH when cleared, is called tpLH. Values for propagation delay from CLR to Q or Q are about 20 ns for LSTTL and 31 ns for high-speed CMOS.
The recovery time, trec, allows the internal logic levels of the flip-flop to reach a steady state after a CLR pulse. When the internal levels are stable, the device is ready to accept an active CLK edge. The recovery time for high-speed CMOS is 20 ns and 25 ns for an LSTTL device. (The LSTTL data sheet treats this parameter as a species of setup time; it is shown as setup time after the CLR is inactive. Same thing.)
Finally, Figure 7.64c shows the propagation delay from CLK to Q. This is the time from the midpoint of an active CLK edge to the midpoint of a transition at Q caused by that CLK edge. The parameters are defined, as before, by the direction of the output transition.
Propagation delays tpLH and tpHL are 20 ns, maximum, for a 74LS107A device and 25 ns for a 74HC107 flip-flop.
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C H A P T E R |
7 • Introduction to Sequential Logic |
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The timing restrictions of a flip-flop imply that there is a maximum CLK frequency be- |
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yond which the device will not operate reliably. Data sheets give these values as about 30 |
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MHz for both LSTTL and high-speed CMOS devices. |
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Table 7.11 summarizes the timing parameters of a 74LS107A flip-flop and a 74HC107 |
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device. The values for the latter device are for Vcc 4.5 V and a temperature range of |
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55°C to 25°C; they increase with a higher temperature range or a lower supply voltage. |
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Table 7.11 Timing Parameters of an LSTTL and a High-Speed |
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Recovery time |
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EXAMPLE 7.11 |
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The timing diagrams in Figure 7.65 represent some of the timing parameters of a JK flip- |
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FIGURE 7.65
Example 7.11
Timing Parameters
SOLUTION The values are as follows:
Setup time 15 ns
Hold time 5 ns
Propagation delays (from CLK): 25 ns (tpLH and tpHL) (from CLR): 20 ns(tpLH and tpHL)
Summary 315
SECTION 7.7 REVIEW PROBLEM
7.7An active edge on the clock input of a JK flip-flop makes Q go from HIGH-to-LOW. Name the timing parameter that measures the delay between the input and output change. Write the symbol for the parameter.
S U M M A R Y
1.A combinational circuit combines inputs to generate a particular output logic level that is always the same, regardless of the order in which the inputs are applied. A sequential circuit might generate different outputs for the same inputs, depending on the sequence in which the inputs were applied.
2.An SR latch is a sequential circuit with SET (S) and RESET
(R) inputs and complementary outputs (Q and Q). By definition, a latch is set when Q 1 and reset when Q 0.
3.A latch sets when its S input activates. When S returns to the inactive state, the latch remains in the set condition until explicitly reset by activating its R input.
4.A latch can have active-HIGH inputs (designated S and R) or active-LOW inputs (designated S and R).
5.Two basic SR latch circuits are the NAND latch and the NOR latch, each consisting of two gates with cross-coupled feedback. In the NAND form, we draw the gates in their DeMorgan equivalent form so that each circuit has ORshaped gates, inversion from input to output, and feedback to the opposite gate.
6.A NOR latch has active-HIGH inputs. It is described by the following function table:
S |
R |
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Qt 1 |
Function |
0 |
0 |
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Qt |
No change |
0 |
1 |
0 |
1 |
Reset |
1 |
0 |
1 |
0 |
Set |
1 |
1 |
0 |
0 |
Forbidden |
7.A NAND latch has active-LOW inputs and is described by the following function table:
S |
R |
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1 |
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1 |
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1 |
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8.A NAND latch can be used as a switch debouncer for a switch with a grounded common terminal, a normally open, and a normally closed contact. When the switch operates, one contact closes, resetting the latch on the first bounce. Further bounces are ignored. When the switch returns to its normal position, it sets the latch on the first bounce and further bounces are ignored.
9.A gated SR latch controls the times when a latch can switch. The circuit consists of a pair of latch gates and a pair of steering gates. The steering gates are enabled or inhibited by a control signal called ENABLE. When the steering gates are enabled, they can direct a set or reset pulse to the latch gates. When inhibited, the steering gates block any set or reset pulses to the latch gates so the latch output cannot change.
10.A gated D (“data”) latch can be constructed by connecting opposite logic levels to the S and R inputs of an SR latch. Since S and R are always opposite, the D latch has no forbidden state. The no change state is provided by the inhibit property of the ENABLE input.
11.In a gated D latch (or transparent latch), Q follows D when ENABLE is active. This is the transparent mode of the latch. When ENABLE is inactive, the latch stores the last value of D.
12.A D latch can be described in VHDL by an IF statement within a PROCESS. The PROCESS statement in VHDL is concurrent, but the statements inside the PROCESS are sequential.
13.A D latch can also be implemented in VHDL by instantiating a LATCH primitive as a component in a VHDL design entity or by instantiating a component called lpm_latch from the Library of Parameterized Modules (LPM).
14.An LPM component is a standard component with certain properties, called parameters, that can be specified when the component is instantiated. The inputs and outputs of an LPM component are called ports. Parameter values are assigned in the generic map of a component instantiation statement. Component port names are associated with user port names in the port map of a component instantiation statement.
15.A flip-flop is like a gated latch that responds to the edge of a pulse applied to an enable input called CLOCK. A flip-flop output will change only when the input makes a transition from LOW to HIGH (for a positive edge-triggered device) or HIGH to LOW (for a negative edge-triggered device).
16.In a positive edge-triggered D flip-flop, Q follows D when there is a positive edge on the clock input.
17.D flip-flops are used primarily for data storage and transfer.
18.A JK flip-flop has two synchronous inputs, called J and K. J acts as an active-HIGH set input. K acts as an active-HIGH reset function. When both inputs are asserted, the flip-flop toggles between 0 and 1 with each applied clock pulse.
19.The toggle function in a JK flip-flop is implemented with additional cross-coupled feedback from the latch gate outputs to the steering gate inputs.
20.A chain of JK flip-flops can implement an asynchronous binary counter if the Q of each flip-flop is connected to the
316 C H A P T E R 7 • Introduction to Sequential Logic
clock input of the next. Although this is an easy way to create a counter, it is seldom used because internal flip-flop delays result in unwanted intermediate states in the count sequence.
21.JK flip-flops can be combined with a network of logic gates to make a synchronous binary counter. The gates are connected in such a way that each flip-flop toggles when all previous bits are HIGH; otherwise the flip-flops are in a no change state. Although more complex than an asynchronous counter, a synchronous counter is free of unwanted intermediate states.
22.Many flip-flops are provided with asynchronous preset (set) and clear (reset) functions. Since these functions are connected directly to the latch gates of a flip-flop, they act immediately, without waiting for the clock. In most cases, these functions are active-LOW.
23.Asynchronous inputs, such as preset and clear, are usually designed so that they will override the synchronous inputs, such as D or JK.
24.Unused asynchronous inputs should be disabled by tying them to a logic HIGH (for an active-LOW input). Flip-flop primitives in MAX PLUS II automatically have their asyn-
chronous inputs connected to HIGH unless otherwise specified by a design entry file.
25.The outputs of a T (toggle) flip-flop toggle with each clock pulse when the T input is HIGH and do not change when T is LOW.
26.Several important timing parameters for a flip-flop include: setup and hold time, propagation delay, minimum pulse width, and recovery time.
27.Setup time is the time before a clock edge that a synchronous input must be held steady. Hold time is the time after an applied clock edge that an input level must be held constant.
28.Propagation delay is the time for an input change, such as on CLK or CLR, to have an effect on an output, such as Q. Propagation time is always indicated with respect to the change in
output level: tpLH for a LOW-to-HIGH output transition and tpHL for a HIGH-to-LOW output change.
29.Minimum pulse width, tw, indicates how long a CLK or CLR input must be held after an active edge or level is applied before returning to the original level.
30.Recovery time is the minimum time required from the end of an active level on one input (such as CLR) to an active CLK edge.
Asynchronous Not synchronized to the system clock.
Asynchronous inputs The inputs of a flip-flop that change the flip-flop’s Q outputs immediately, without waiting for a pulse at the CLK input. Examples include preset and clear inputs.
Clear An asynchronous reset function.
CLOCK An enabling input to a sequential circuit that is sensitive to the positiveor negative-going edge of a waveform.
Edge The HIGH-to-LOW (negative edge) or LOW-to-HIGH (positive edge) transition of a pulse waveform.
Edge detector A circuit in an edge-triggered flip-flop that converts the active edge of a CLOCK input to an active-level pulse at the internal latch’s SET and RESET inputs.
Edge-sensitive Edge-triggered.
Edge-triggered Enabled by the positive or negative edge of a digital waveform.
Flip-flop A sequential circuit based on a latch whose output changes when its CLOCK input receives either an edge or a pulse, depending on the device.
Gated SR latch An SR latch whose ability to change states is controlled by an extra input called the ENABLE input.
Generic map A VHDL construct that maps one or more parameters of a component to a value for that instance of the component.
Hold time (th) The time that the synchronous inputs of a flip-flop must remain stable after the active CLK transition is finished.
Latch A sequential circuit with two inputs called SET and RESET, which make the latch store a logic 0 (reset) or 1 (set) until actively changed.
Level-sensitive Enabled by a logic HIGH or LOW level.
Library of Parameterized Modules (LPM) A standardized set of components for which certain properties can be specified when the component is instantiated.
Master Reset An asynchronous reset input used to set a sequential circuit to a known initial state.
Parameter (in an LPM component) A property of a component that can be specified when the component is instantiated.
Preset An asynchronous set function.
Port map A VHDL construct that maps the name of a port in a component to the name of a port, variable, or signal in a design entity that uses the component.
Propagation delay The time required for the output of a digital circuit to change states after a change at one or more of its inputs.
Pulse width (tw) Minimum time required for an active-level pulse applied to a CLK, CLR, or PRE input, as measured from the midpoint of the leading edge of the pulse to the midpoint of the trailing edge.
Recovery time (trec) Minimum time from the midpoint of the trailing edge of a CLR or PRE pulse to the midpoint of an active CLK edge.
Reset 1. The stored LOW state of a latch circuit. 2. A latch input that makes the latch store a logic 0.
Sequential circuit A digital circuit whose output depends not only on the present combination of inputs, but also on the history of the circuit.
Set 1. The stored HIGH state of a latch circuit. 2. A latch input that makes the latch store a logic 1.
Setup time (tsu) The time required for the synchronous inputs of a flip-flop to be stable before a CLK pulse is applied.
318 C H A P T E R 7 • Introduction to Sequential Logic
The motor is housed in a safety enclosure that has an access hatch for service. A safety interlock prevents the motor from running when the hatch is open. The HATCH switch opens when the hatch opens, supplying a logic HIGH to the circuit. The START switch is a normally open momentary-contact pushbutton (LOW when pressed). The STOP switch is a normally closed momen- tary-contact pushbutton (HIGH when pressed).
Draw the timing diagram of the circuit, showing START, STOP, HATCH, S, R, and Q for the following sequence of events:
a.START is pressed and released.
b.The hatch cover is opened.
c.START is pressed and released.
d.The hatch cover is closed.
e.START is pressed and released.
f.STOP is pressed and released.
Briefly describe the functions of the three switches and how they affect the motor operation.
Section 7.2 NAND/NOR Latches
7.5Draw a NAND latch, correctly labeling the inputs and
outputs. Describe the operation of a NAND latch for all four possible combinations of S and R.
7.6Draw a NOR latch, correctly labeling the inputs and outputs. Describe the operation of a NOR latch for all four possible combinations of S and R.
7.7The timing diagram in Figure 7.70 shows the input waveforms of a NAND latch. Complete the diagram by showing the output waveforms.
FIGURE 7.70
Problem 7.7
Timing Diagram
FIGURE 7.71
Problem 7.8
Input Waveforms to a NOR
Latch
FIGURE 7.72
Problem 7.9
Input Waveforms to a Latch
7.8Figure 7.71 shows the input waveforms to a NOR latch. Draw the corresponding output waveforms.
7.9Figure 7.72 represents two input waveforms to a latch circuit.
a.Draw the outputs Q and Q if the latch is a NAND latch.
b.Draw the output waveforms if the latch is a NOR latch.
(Note that in each case, the waveforms will produce the forbidden state at some point. Even under this condition, it is still possible to produce unambiguous output waveforms. Refer to Figures 7.18 and 7.19 for guidance.)
7.10a. Draw a timing diagram for a NAND latch showing each of the following sequences of events:
i.S and R are both LOW; S goes HIGH before R.
ii.S and R are both LOW; R goes HIGH before S.
iii.S and R are both LOW; S and R go HIGH simultaneously.
b.State why S R 0 is a forbidden state for the NAND latch.
c.Briefly explain what the final result is for each of the above transitions.
7.11a Draw a timing diagram for a NOR latch showing each of the following sequences of events:
i.S and R are both HIGH; S goes LOW before R.
ii.S and R are both HIGH, R goes LOW before S.
iii.S and R are both HIGH, S and R go LOW simultaneously.
