Digital design with CPLD applications and VHDL (R. Dueck, 2000)

350 C H A P T E R 8 • Introduction to Programmable Logic Architectures

FIGURE 8.18

GAL22V10 Logic Diagram

1.There are more outputs (10 as opposed to 8 for the 16V8).

2.There are more inputs (11 dedicated inputs, plus any I/O lines used as inputs).

3.The output logic macrocells are of different sizes, allowing expressions with larger numbers of product terms in some OLMCs than others. There are two OLMCs with each of the following numbers of product lines: 8, 10, 12, 14, and 16. This allows more flexibility in design, while minimizing the number of product lines.

FIGURE 8.19

GAL22V10 OLMC Configurations

4.OLMC configuration is much simpler than that of a PALCE16V8. Two architecture cells per macrocell, S0 and S1, select the output type, as shown in Figure 8.19.

5.There are product lines for Synchronous Preset (SP) and Asynchronous Reset (AR). The SP line sets all flip-flops HIGH on the first clock pulse after it becomes active. The AR line sets all flip-flops LOW as soon as it activates, without waiting for the clock pulse. (Note that these lines set or reset the Q output of each flip-flop. An active-LOW registered output inverts this state at the output pin.)

8.6MAX7000S CPLD

K E Y T E R M S

CPLD Complex programmable logic device. A programmable logic device consisting of several interconnected programmable blocks.

Logic Array Block (LAB) A group of macrocells that share common resources

in a CPLD.

Programmable Interconnect Array (PIA) An internal bus with programmable connections that link together the Logic Array Blocks of a CPLD.

The main structure of the MAX7000S is a series of Logic Array Blocks (LABs), linked by a Programmable Interconnect Array (PIA). Each LAB is a group of 16 macrocells that can share common product terms and lend or borrow unused product terms among each other. A single LAB has similar I/O and programming capability to a low-density PLD, so a CPLD like the MAX7000S can be thought of as an array of interconnected PALs or GALs on a single chip.

An EPM7128S has 8 LABs, for a total of 8 16 128 macrocells. However, these are not all available to the user as I/Os; the number of available I/O pins depends on the device package. Figure 8.20 indicates that each LAB in a MAX7000S device has from 6 to 16 I/O pins. For an EPM7128S in a 160-pin PQFP package, there are 12 I/Os per LAB, for a total of 96 available pins. For the same device in an 84-pin PLCC package, there are only 8 I/Os per LAB, for a total of 64 pins.

In practice, if an EPM7128SLC84 is to be programmed in-circuit (i.e., while installed on a circuit board), there are only 60 I/Os available, as four pins are required for the programming interface. The macrocells that are not connected to user I/O pins can only be used for buried logic, or logic that is internal to the chip only.

As implied in Figure 8.20, all I/O pins connect to and from their associated LAB via an I/O Control Block (a circuit that controls the tristate switching of signals at an I/O pin). The I/O pin signals also connect directly to the PIA, where they are available for use in other LABs. Sixteen lines connect the macrocell outputs of each LAB to the PIA, again for use throughout the device. The PIA communicates to each LAB via 36 product lines to provide connections from other LABs.

The MAX7000S family has four pins that can be configured as control signals or inputs. GCLK1 is a global clock that is common to all macrocells in the device and can be used to synchronously clock all registers. OE1 is an output enable that can globally activate or disable the tristate outputs of the device macrocells. GCLRn is an activeLOW global clear function. The fourth control pin can be configured as an input, as can the other three pins, or as a second global clock (GCLK2) or output enable (OE2). If the control functions are not used, these pins add four inputs to the available total. These assignments can be made by the MAX PLUS II software during the design process.

Figure 8.21 shows a macrocell from a MAX7000S device. The macrocell is similar to that of a GAL or Universal PAL in that it provides a sum-of-products function with activeHIGH or -LOW options and the choice of registered or combinational output. Registered outputs can be clocked with one of two global clocks or by a product term from the AND matrix. The register can be cleared globally or by a product term and preset with a product term.

The macrocell has five dedicated product terms, which is fewer than found in the PAL and GAL matrices we examined earlier. This is generally sufficient to implement most logic functions. If more terms are required, they can be supplied by a set of shared logic expanders or parallel logic expanders.

Shared logic expanders do not add more product terms to a given macrocell. They do make the programming of the entire LAB more efficient by allowing a product term to be programmed once and used in several macrocells of the same LAB. One product term per macrocell is inverted and fed back into the shared expander pool of product terms. Since there are 16 macrocells per LAB, the shared logic expander pool has up to 16 product terms.

Parallel logic expanders allow a macrocell to borrow up to 15 product terms from its three lower-numbered neighbors (5 product terms per neighboring macrocell). For example, macrocell 4 can borrow up to 5 terms each from macrocells 3, 2, and 1. By using its 5 dedicated product terms and the maximum number of parallel expanders, a macrocell can have up to 20 product terms at its disposal. These borrowed terms are not usable by the macrocell from which they were borrowed. The parallel expanders are set up so that a lower-number cell lends product terms to a higher-number cell, so the number of available terms depends on how close to the end of a chain a macrocell is. Expander assignments are done automatically by MAX PLUS II at compile time.

354 C H A P T E R 8 • Introduction to Programmable Logic Architectures

FIGURE 8.21

MAX 7000E and MAX 7000S Device Macrocell (Courtesy of Altera)

8.7 FLEX10K CPLD

K E Y T E R M S

Look-up table (LUT) A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations.

Logic element (LE) A circuit internal to a CPLD used to implement a logic function as a look-up table.

Cascade chain A circuit in a CPLD that allows the input width of a Boolean function to expand beyond the width of one logic element.

Carry chain A circuit in a CPLD that is optimized for efficient operation of carry functions between logic elements.

Embedded array block (EAB) A relatively large block of storage elements in a CPLD (2048 bits in a FLEX10K device), used for implementing complex logic functions in look-up table format.

All programmable logic devices we have seen until now have been based on sum-of- products arrays. Another major type of PLD is based on look-up table (LUT) architecture. In this architecture, a number of storage elements are used to synthesize logic functions by storing each function as a truth table. To illustrate the look-up table concept, let us use the truth table of a 2-bit equality comparator, shown in Table 8.2.

The comparator examines inputs A1A0 and B1B0 and makes output AEQB equal to logic 1 if A1A0 B1B0. If we were to implement the circuit as an SOP array, we would first find the Boolean expression by combining the four product terms from the truth table and then program the appropriate cells in a CPLD AND matrix. The look-up table implementation of this function is based on a totally different concept.

FIGURE 8.23

FLEX10K Logic Element (Courtesy of Altera)

FIGURE 8.24

Cascade Chain Operation (Courtesy of Altera)