Digital design with CPLD applications and VHDL (R. Dueck, 2000)

FIGURE 5.7

Example 5.3

Address Decoder for a Memory System

whole system can hold 8 8192 65,536 (64K) bytes. (Although this amount of memory may seem small by the standards of a desktop computer, it may be typical of a small stand-alone computer system (called an embedded system or a microcontroller) that is used in control applications.)

Each 8K block is enabled by a LOW at its G input. Briefly explain the function of the decoder in the system.

Solution Since only one decoder output is LOW at any one time, the decoder allows only one memory block to be active at any one time. The active block is chosen by inputs ADDR15 ADDR14 ADDR13, which are connected to D2D1D0 on the decoder. The active memory block is the one connected to the y output whose subscript matches the binary value of these inputs. For example, when ADDR15 ADDR14 ADDR13 110, the block connected to y6 is active.

If the decoder is the same as the one in Figure 5.6, no outputs will be active, and therefore no memory block will be enabled, when G 1. (Note that the MAX PLUS II Graphic Editor cannot represent an input or output with an inversion bar. Some conventions would represent an active-LOW terminal with an “n” prefix, indicating “NOT” (e.g., nG). This is a matter of personal choice, but without such an indication it is not possible to tell the active level of an input or output from the MAX PLUS II Graphic Design File.)

The decoders in Figure 5.6 and 5.7 have identical functions, but the symbol in Figure 5.7 shows the D inputs and Y outputs as multibit vectors or busses. Figure 5.7 also shows how the individual signals in a bus can be connected to separate parts of the circuit in a MAX PLUS II Graphic Design File.

To make the connections, draw and label a line extending from each terminal. To label a line, highlight the line by clicking on it with the left mouse button, then right-click. Select Enter Node/Bus Name from the pop-up menu and enter the text. Lines that have the same names are automatically connected by their text references. If a line is a multiple line,

We specify the inputs and outputs we want to view by selecting Enter Nodes from SNF on the Node menu, shown in Figure 5.9. In the dialog box that pops up (Figure 5.10), there are two boxes labelled Available Nodes & Groups and Selected Nodes & Groups, with an arrow ( ) pointing from one to the other. Select the List button to show the “available” signals and click the arrow to transfer them all to the “selected” box. Click OK to close the box.

FIGURE 5.9

Node Menu

FIGURE 5.10

Selecting Nodes for Waveform

Editor

Figure 5.11 shows the simulation waveforms in their uninitialized (default) states. Inputs and outputs are shown by symbols in front of the signal names. Inputs are at logic 0 and outputs are indicated as X or unknown values.

FIGURE 5.11

Default Values of Simulation Waveforms

because it corresponds to one half period of the oscillator on the Altera UP-1 board. In the simulator, one full period requires two grid spaces.)

When we created the simulation file, the D inputs were entered as separate waveforms. We can join these waveforms to make a Group. Highlight both D1 and D0 by clicking on one name and dragging the mouse to the next name, as in Figure 5.16. From the Node menu or the pop-up menu in Figure 5.17, select Enter Group. The dialog box shown in Figure 5.18 appears, containing the most likely name derived from the highlighted group. Either type a new group name or accept the original name by clicking OK.

FIGURE 5.16

Highlighting a Group

FIGURE 5.17

Pop-up Menu (Enter Group)

FIGURE 5.18

Enter Group Dialog Box

168 C H A P T E R 5 • Combinational Logic Functions

In addition to coding the Boolean expressions directly, we can use two types of concurrent signal assignments to create decoder circuits: the selected signal assignment statement and the conditional signal assignment statement. Both the Altera VHDL manual and the Help menu in MAX PLUS II have a section on “Golden Rules” for VHDL. The VHDL Golden Rules suggest that you should use a selected signal assignment rather than a conditional signal assignment, if possible. This is because, in certain cases, the selected signal assignment uses the internal circuitry of the CPLD more efficiently.

The selected signal assignment has the form:

label: WITH __expression SELECT

__signal <=__expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value;

The signal indicated in the second line of the statement template is assigned one of several expressions, depending on the constant value of the expression in the first line. The label is optional. Examine the selected signal statement below:

Signal y is assigned one of three values, p, q, or not q, depending on the status of a two-bit variable called mode. Note that the value of y for the case when mode “10” is not explicitly stated. This is covered by the last clause (WHEN others), which defines a default value for signal y of logic 1.

The following VHDL code implements a 2-line-to-4-line decoder using a selected signal assignment statement.

decode3.vhd

END decode3;

ARCHITECTURE decoder OF decode3 IS

BEGIN

WITH d SELECT

y <= “0001” WHEN “00”, “0010” WHEN “01”, “0100” WHEN “10”, “1000” WHEN “11”, “0000” WHEN others;

END decoder;

The selected signal assignment statement evaluates input d. For every possible combination of the 2-bit input vector, d, a particular value is assigned to the 4-bit vector, y. (For

example, for the case d1d0 10 ( 210), the output y2 is HIGH: y3y2y1y0 0100.)

The default case (“WHEN others”) is required because of the multivalued logic type STD_LOGIC_VECTOR. Since a STD_LOGIC_VECTOR can have values other than ‘0’ and ‘1’, the values listed for d don’t cover all possible cases. The default output (which will never occur if we only use ‘0’ and ‘1’ inputs) is chosen such that no output is active in the

default case. The default case would not be required if we chose to use BIT_VECTOR, rather than STD_LOGIC_VECTOR, since the listed combinations of d cover all possible combinations of a BIT_VECTOR. However, it is a good practice to include the default case, in order to account for all possible contingencies.

In order to include an enable input (g) in a decoder, we can increase the input vector size to include the g input, as shown in the following code.

END decode3a;

ARCHITECTURE decoder OF decode3a IS

SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0);

To include g and d in a single vector, we create a signal called inputs, a vector with three elements in the sequence g, d(1), d(0). When assigning the d to the last two elements of inputs, we must be explicit about which elements of inputs we want to use. Since d only contains two elements and we are assigning them to two elements of inputs, we don’t need to list the elements of d explicitly.

We can use a selected signal assignment statement to evaluate all inputs, including g , and assign outputs accordingly. When g ‘0’, the decoder outputs are assigned the same as they were in the example without the enable input. The cases where g ‘1’ are covered by the others clause. In this default case, all decoder outputs are LOW (inactive).

Another way to include an enable input is to use a conditional signal assignment statement, which makes an assignment based on a Boolean expression. This template for the conditional signal assignment statement is:

__signal <= __expression WHEN __boolean_expression ELSE

__expression WHEN __boolean_expression ELSE

__expression;

The first Boolean expression in the statement is evaluated. If it is true, the corresponding expression is assigned to the signal. If false, the next Boolean expression is evaluated, and so on until a true Boolean expression is found. If none are true, the signal is assigned a default expression, listed last in the statement.

The VHDL code below implements the decoder with an active-LOW enable. If g is LOW, one decoder output activates, depending on the value of d. Note that the d inputs are defined as type INTEGER, rather than BIT_VECTOR or STD_LOGIC_VECTOR. In this situation, we don’t need to specify the number of inputs; the compiler automatically defines the required inputs d1 and d0 when fitting the design to the selected CPLD. Also, since d is of type INTEGER, we write its value in the selected signal assignment statement directly, without quotes.