Digital design with CPLD applications and VHDL (R. Dueck, 2000)

132 C H A P T E R 4 • Introduction to PLDs and MAX+PLUS II

4.26

of Hierarchy (4votes.gdf)

beled maj vote, the MAX PLUS II Graphic Editor will bring the file maj_vote.gdf to the foreground. Thus, we say that 2votes.gdf is at the top level of the current hierarchy.

We can extend the hierarchy further by making a symbol for 2votes.gdf and embedding it in a higher-level file called 4votes.gdf, shown in Figure 4.26. This circuit generates a HIGH output if (two out of three of (A11, B11, C11) are HIGH AND two out of three of

FIGURE 4.27

Hierarchy Display for Project “4votes”

(A21, B21, C21) are HIGH) OR the same is true for (A12, B12, C12) AND (A22, B22, C22). If we double-click on either symbol for 2votes, the Graphic Editor will bring the file 2votes.gdf to the foreground.

MAX PLUS II can display the hierarchy of a design. To see the hierarchy structure, click the Hierarchy icon on the MAX PLUS II toolbar (the yellow pyramid) or choose Hierarchy Display from the MAX PLUS II menu. Figure 4.27 shows the hierarchy for the project 4votes. Note that the highest level has two subdesigns, each of which breaks down further into two subdesigns. Thus, using hierarchical design and symbols for gdf or other design files allows us to create multiple instances of a basic design (maj_vote.gdf) and use it in many places.

N O T E

In order to correctly show the hierarchy display, the top-level file of the project (in this case 4votes.gdf) must be compiled first.

4.6 Text Design File (VHDL)

K E Y T E R M S

Hardware description language A computer language used to design digital circuits by entering text-based descriptions of the circuits.

puter language used to model digital circuits and produce programming data for PLDs.

VHSIC Very high speed integrated circuit

Syntax The “grammar” of a computer language. (i.e., the rules of construction of language statements)

ASICs (application specific integrated circuits) Integrated circuits that are constructed for a specific design purpose. The term could refer to a PLD, although it usually means a custom-designed fixed function device.

An alternative to schematic entry, and ultimately a more powerful PLD design technique is the use of a text-based design tool, or hardware description language, such as Altera’s

AHDL (Altera Hardware Description Language) or the industry-standard VHDL (VHSIC Hardware Description Language). A designer creates a text file, framed within a certain set of rules known as the syntax of the language and uses a compiler to create pro-

134 C H A P T E R 4 • Introduction to PLDs and MAX+PLUS II

gramming data much as he or she would with a Graphic Design File. Hardware description languages can be used to generate hardware for hierarchical designs, either as components in graphic or text files or as higher level design entities containing other designs.

AHDL, while very easy to use, has a much narrower application than VHDL because it is one of many proprietary tools on the market aimed at the programming requirements of a particular manufacturer’s line of CPLDs. Since VHDL is an industry-standard language and the MAX PLUS II compiler supports both languages, we will concentrate on VHDL.

VHDL was originally developed by defense contractors in the U.S. and is now the required standard for all ASICs (application specific integrated circuits) designed for the U.S. military. It has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) and has been enjoying increasing popularity in the electronics design community. The original VHDL standard was written in 1987 and updated in 1993 (IEEE Std. 1076-1993). This standard and other related ones continue to undergo revision. The current status of Std. 1076 can be determined from the IEEE Standards web site at http://www.standards.ieee.org.

Entity and Architecture

K E Y T E R M S

Entity A VHDL structure that defines the inputs and outputs of a design.

Architecture A VHDL structure than defines the relationship between input, output, and internal signals or variables in a design.

Port A name assigned to an input or output of a VHDL design entity.

Mode (of a port) The kind of port, such as input or output.

Signal A name given to an internal connection in a VHDL architecture.

Variable A block of working memory used for internal calculation or storage in a

VHDL architecture.

Type A set of characteristics associated with a VHDL port name, signal, or variable that determines the allowable values of the port, signal, or variable.

Library A collection of VHDL design units that have been previously compiled.

Package A group of VHDL design elements that can be used by more than one

VHDL file.

IEEE Standard 1164 The standard which defines a variety of VHDL types and operations, including the STD_LOGIC and STD_LOGIC_VECTOR types.

Concurrent Simultaneous.

Concurrent signal assignment A relationship between an input and output port or signal in which the output is changed as soon as there is a change in input. If the file has more than one concurrent signal assignment, they are all evaluated simultaneously.

Selected signal assignment statement A concurrent signal assignment in VHDL in which a value is assigned to a signal, depending on the alternative values of another signal or variable.

Comment Explanatory text in a VHDL (or other computer language) file that is ignored by the computer at compile time.

Vector A group of digital signals or variables, usually related numerically, that can be treated as a single multibit variable.

Bit string literal A group of bits assigned to the elements of a vector, enclosed in double quotes (e.g., “001011”).

136 C H A P T E R 4 • Introduction to PLDs and MAX+PLUS II

FIGURE 4.29

VHDL Port Modes

a change in one input that is common to several circuits makes all circuits change at the same time.

Enclosed in the entity declaration is a port definition. A port is a connection from the PLD to the outside world. Figure 4.29 shows the possible modes of a port. Mode IN refers

BUFFER

FIGURE 4.30

BUFFER and OUT Modes

to a port that is only for input. Mode OUT is output only. Mode INOUT is a bidirectional port, in which data can flow in either direction, based on the status of a control input. Mode BUFFER is a special case of OUT that has a feedback connection back into the CPLD logic that can be used as part of another Boolean expression.

Figure 4.30 shows the difference between BUFFER and OUT modes. Port x (defined by x <= a and b;) must be of mode BUFFER because it is fed back and used as part of the expression for port y (defined by y <= x or c;). Port y can be of mode OUT since it has no feedback, only an output.

In addition to defining the port modes, the entity declaration also defines what type each port is. The type of a port, signal, or variable defines what values it is allowed to have. Three common types in VHDL are BIT, STD_LOGIC, and INTEGER. Multibit extensions of these types include BIT_VECTOR and STD_LOGIC_VECTOR.

Ports, signals and variables of type BIT can have a value of ‘0’ or ‘1’. When using these values, they must be enclosed in single quotes.

The STD_LOGIC (standard logic) type, also called IEEE Std.1164 Multi-Valued Logic, has been defined to give a broader range of output values than just ‘0’ and ‘1’. Any port, signal, or variable of type STD_LOGIC or STD_LOGIC_VECTOR can have any of the values listed below.

‘U’, –– Uninitialized ‘X’, –– Forcing Unknown ‘0’, –– Forcing 0

‘1’, –– Forcing 1 ‘Z’, –– High Impedance

—— Makes one and only one output HIGH for each

—— binary combination of (d1, d0).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY decode2a IS

PORT (

d : IN STD_LOGIC_VECTOR (1 downto 0); y : OUT STD_LOGIC_VECTOR (3 downto 0));

END decode2a;

ARCHITECTURE decoder OF decode2a IS

BEGIN

——Choose a signal assignment for y

——based on binary value of d

——Default case: all outputs deactivated WITH d SELECT

y <= “0001” WHEN “00”, “0010” WHEN “01”, “0100” WHEN “10”, “1000” WHEN “11”, “0000” WHEN others;

END decoder;

In Case 3, we use a selected signal assignment statement to assign a value to all bits of vector y for each combined value of vector d. For example, when d(1) 0 and d(0) 0, the values assigned to y are: y(3) 1, y(2) 0, y(1) 0, y(0) 0. Similar assignments are made for other values of d. The result is a construct that acts much like a truth table of the decoder circuit. The others clause is necessary to define a default case

FIGURE 4.32

MAX PLUS II Template Menu

FIGURE 4.33

VHDL Template Dialog Box