3troubleshootingjunos

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I-Chip Ov rvi w

Inheriting all the f atur

s of the LMNR chips, the I-chip is the Juniper Networks

next-generation Int rn

processor delivering PFE on a chip. Each I-chip can send

20 Gbps of bandwidth to the fabric and can receive 17 Gbps of bandwidth from the

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fab ic. The I-chip’s flexibility comes through programmability, a rich instruction set,

and silicon development. Various Juniper Networks platforms deploy the I-chip,

including the M120, the MX Series, and the SRX Series.

New Capabilities

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The I-chip provides industry-leading scalability, allowing significant headroom in

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Deterministic Performance

The J Series Routing Engine and software PFE both implement on the primary x86

architecture microproc ssor. A al-time operating system kernel mediates access to

the underlying hardware. The real-time kernel ensures that operating system services

forwarding

delive y occu s in a constant, load-independent, amount of time. This process ensures

that the fo wa ding and services real-time threads deliver predictable packet

forwa ding pe fo mance.

C ntr l and Forwarding Separation

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Separate real-time processes maintain logical separation between the control plane

and

plane. Control plane processes continue to run on the traditional

When you install an FPC into a running system, the FPC requests its operating

forsoftware from the Routing Engine, runs its diagnostics, and enables its PICs on the

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FPC slot. FPCs are hot-swappable on all platforms except the M7i and the M10i

because these routers have FPCs that combine with the system board components to

create a CFEB. The CFEB on the M7i and the M10i is hot-insertable but not

hot-removable.

Note that when you remove or install an FPC on an M Series router, the system must

re-partition the shared memory pool; this process results in about 200 milliseconds of

disruption to all packets associated with the affected PFE. T Series platforms contain

from one to two complete PFEs on each FPC, and therefore removal or insertion of

FPCs does not affect packet forwarding on other FPCs.

ABC chipset-based routers have an aggregate slot throughput

f 6.4 Gbps. LMNR

chipset-based platforms increase aggregate slot throughput

a respectable 20 Gbps

for the M120, 40 Gbps for the M320 an the T320, and 80

Gbps for the T640.

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MX Series Dense Port Conc ntrators

All DPCs come in eith a small form-factor pluggable transceiver (SFP) or a 10-gigabit

small form-factor pluggable transc iver (XFP), which uses the most optimal port

density with cost efficiency. Each DPC has connections to the switch fabric providing

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lineate connectivity for each port on the card.

DPCs p ovide multiple physical interfaces and PFEs on a single board that installs in a

sl t in the MX Se ies router. A DPC receives incoming packets from the network and

sends utg ing packets to the network. Each DPC contains four PFEs. The PFEs on a

DPC have purpose-built ASICs that perform packet processing and forwarding. Each

PFE c nsists one I-chip for Layer 3 processing and one Layer 2 network processor.

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Multiple PFEs contribute to the system’s full packet forwarding redundancy and

resiliency.

SPCs andReproductionREs are separate—both physically and logically. This separation of

the

Service Proc

ssing Cards

SPCs are blad

s that provide the capacity to perform the heavy lifting of processing

network pack ts. The chassis must have at least one SPC to operate. You realize the

true elegance of this design when your system has more than one SPC installed.

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Rather than the chassis having two or more “brains”, as in traditional network

a chitecture, the addition of a new SPC essentially results in a larger system that can

pe m many more tasks at a given time. To ensure the highest level of reliability, the

c ntr l and data planes ensures that a fault on any of the SPCs does not result in

catastrophic failure of the entire chassis. You can see the importance of this concept

in a security situation such as a denial of service (DoS) attack. When the attack

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n a given PIC vaReproductionies with the PIC and platform type. For example, M40e PICs

are

PIC Overview

PICs provide the physical conn ction to various network media types. PICs receive

incoming packets from the twork and transmit outgoing packets to the network.

During this process, each PIC performs appropriate framing and signaling for its

media type. Befo e transmitting outgoing data packets, the PIC adds media-specific

framing to the packets received from the FPCs. You can install up to four PICs into

slots on each FPC. PIC types can intermix within the same FPC. The number of ports

available with as many as 48 Fast Ethernet ports.

IP services PICs enable a hardware assist for complex packet processing functions.

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Examples include the tunnel services and multilink services PICs. With the tunnel

forservices PIC, routers can function as the ingress or egress point of an IP over IP

(excludes the M320, which is based

a T Series PFE). This momentary disruption is

the result of the FPC underg ing a l gical reset in reaction to the insertion and

removal of a PIC. Failing to take a PIC

fflin before removing it from its FPC can result

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