3troubleshootingjunos
.pdf
Troubleshooting JUNOS Platforms
SRX Series Architecture (contd.)
If the RE is the central nervous system of the chassis, the SPC is the brain. SPCs are blades that provide the capacity to perform the heavy lifting of processing network packets. The chassis must have at least one SPC to operate.
|
The chassis slots are card-agnostic, allowing you to configure the architecture for their |
|
|
specific needs up to the limits of the chassis itself. Based on the agnostic design, the |
|
|
|
Reproduction |
|
IOCs can scale independently. |
|
Not |
for |
|
|
|
|
Overview of JUNOS Platforms • Chapter 2–37
Troubleshooting JUNOS Platforms
Not
JUNOS SoftwareReproduction
The primary copy of JUNOS Software resides the flash memory of the JUNOS device. A backup copy is available on the hard disk when you issue a request system snapshot command.
forRouting Engine Intelligence
The RE handles all the routing protocol processes as well as other software processes that c ntr l the interfaces on the device. It also handles a few of the chassis
c mp nents, system management, and user access to the device. These routing and so tware processes run on top of a kernel that interacts with the PFE. JUNOS Software directs all routing protocol packets from the network to the RE.
Command-Line Interface
The RE provides the command-line interface (CLI). The CLI runs on top of the kernel; the management process (mgd) controls it.
Continued on next page.
Chapter 2–38 • Overview of JUNOS Platforms
Troubleshooting JUNOS Platforms
Packet Forwarding Engine Management
The RE controls the PFE by providing an accurate and up-to-date forwarding table and by downloading microcode and managing software processes that live in the PFE’s microcode. The RE receives hardware and environmental status messages from the PFE and acts upon them as appropriate.
|
for |
Reproduction |
Not |
|
|
|
|
Overview of JUNOS Platforms • Chapter 2–39
Troubleshooting JUNOS Platforms
Custom ASICs
ASICs enable the rout to achi |
ve data forwarding rates that match current fiber-optic |
capacity. The router achi v s th |
se rates by distributing packet processing tasks |
across highly integrated ASICs. As a result, ASICs-based JUNOS platforms do not |
|
requi e a gene al purpose processor for packet forwarding. The custom ASICs provide |
|
enhanced se vices and features, such as multicast, class of service (CoS) and |
|
queuing, and fi ewall filtering in hardware so that you can enable services on |
|
pr ducti n devicesReproductionwithout concern of significant performance hits. Each ASIC |
|
pr vides a piece of the forwarding puzzle, allowing a single ASIC to perform its specific |
|
task ptimally. |
|
forReal-Time Threads |
|
Not |
|
Real-time operating systems give guaranteed processor cycles to each real-time thread. Careful designers can guarantee that the processor never becomes oversubscribed. As a result, these threads have the same benefits as ASICs, albeit at a lower total performance capability.
Chapter 2–40 • Overview of JUNOS Platforms
Not
Troubleshooting JUNOS Platforms
The MidplaneReproduction
The system midplane is the component of the PFE that distributes power and electrical signals to ach card in the system. Typically the midplane is passive in JUNOS platforms.
forSystem Control Boards
On M Se ies platforms, the System Control Boards provide the route lookup
c mponent of the PFE using the Internet Processor II ASIC. Each System Control Board n M Series routers provides the same function, despite each having different names.
On the M7i and M10i, the FPC and Control Board components combine onto a single board named the Compact Forwarding Engine Board (CFEB). On the M7i and M10i, the Fixed Interface Card (FIC) or High-Availability Chassis Manager (HCM) perform chassis control functions, such as PIC online and offline and chassis monitoring, respectively. The M Series System Control Board—FEB, CFEB, or Switching and Forwarding Module (SFM)—also houses the buffer management ASICs on all models.
Continued on next page.
Overview of JUNOS Platforms • Chapter 2–41
Troubleshooting JUNOS Platforms
Not
General System Board Functions
The system board functions of JUNOS platforms deploying ABC chipsets include forwarding table updates and route lookup, system control, PFE clock generation, exception packet and control packet handling, and environmental monitoring:
•Route lookups and forwarding table maintenance: The Internet
|
Reproduction |
||
|
Processor ASIC performs route lookups using a forwarding table stored in |
||
|
the chip’s SSRAM. The System Board updates its copy of the forwardi g |
||
|
table when instructed by the JUNOS Software kernel. |
|
|
• |
Management of ASICs and PFE components: The System B ard m |
it rs |
|
|
various system components for failures and alarm cond t |
ns. It c |
llects |
|
statistics from all sensors in the system and relays hem |
he RE, which |
|
|
sets the appropriate alarm. For example, if a tempera ure sens r exceeds |
||
|
the first internally defined threshold, the RE issues a h gh |
emp alarm. |
|
|
The System Board handles the power on and power off of PFE |
|
|
|
components with diagnostic errors reported to the RE over the 100 Mbps |
||
|
fxp1 interface. |
|
|
• |
Environmental monitoring: The System Board monitors the various |
|
|
|
temperature sensors to control fan speed and over-temperature alarm |
||
|
generation. |
|
|
• |
SONET clock: The System B ard generates a Stratum 3 clock reference |
||
|
used to clock SONET inte faces. |
|
|
• |
Transfer of exception and nt l packets: The Internet Processor ASIC |
||
|
passes exception ackets to a microprocessor on the System Board, |
||
|
which processes almost all of them. JUNOS Software sends the |
|
|
|
remaining pack ts to the RE for further processing. If the System Board |
||
|
detect rrors originating in the PFE, the software logs them and makes |
||
|
them available to the CLI. |
|
|
Flexible PIC Concentrator
forFPCs house the PICs and provide shared memory for the M Series switch fabric. These intelligent, high-performance interface concentrators allow you to mix and match PIC types within a given FPC.
Physical Interface Cards
Juniper Networks M Series routers provide a complete range of fiber-optic and electrical transmission interfaces to the network through a variety of PICs. These space-efficient modules offer exceptional flexibility and high port density.
Chapter 2–42 • Overview of JUNOS Platforms
Not
Troubleshooting JUNOS Platforms
Reproduction |
|
|
||
|
||||
Physical Int rface Cards |
||||
As with the M S |
ri |
s rout rs, PICs provide T Series PFEs with a large range of |
||
fiber-optic and |
l |
ctrical transmission interfaces to the network. |
||
forThe T Series PFE
T Se ies outers implement either one or two complete PFE complexes each FPC. On the T640 a single PFE is present on FPC2 while two PFEs are present on FPC3. We designed the latter FPC type specifically for native T Series PICs. Packets that ingress and egress on the same PFE complex (for example, on PICs 0 and 1 or PICs 2 and 3 of a given FPC) do not leave that PFE. The SIBs switch packets between PFEs across the T Series switch fabric as needed.
Continued on next page.
Overview of JUNOS Platforms • Chapter 2–43
Troubleshooting JUNOS Platforms
The T Series Switch Fabric
T Series routers make use of a shared memory switch fabric for communications between and across FPCs and PFEs. In addition, inter-FPC communications require transit of the T Series crossbar switch fabric, which the system’s SIBs represent. The T320 can support up to three SIBs, while the T640 supports five. In the case of the
T640, four SIBs provide the necessary speedup for a nonblocking architecture. The fifth SIB comesReproductioninto use only in the event of a SIB failure. The system’s throughput gracefully degrades in the unlikely event of multiple SIB failures. In normal operatio ,
the T320 makes use of SIBs 1 and 2 with SIB 0 functioning as a standby. In the eve of a SIB failure, SIB 0 automatically becomes active. There might be a slight performance degradation when using SIB 0 because each FPC has only ne high-speed line to SIB 0 (two high-speed lines interconnect the FPCs f SIB 1 and SIB 2).
The Midplane
The midplane distributes power and electrical signals to the omponents and cards that make up the PFE and the switch fabric.
Not |
for |
|
Chapter 2–44 • Overview of JUNOS Platforms
Not
Troubleshooting JUNOS Platforms
The M320ReproductionFPC and Switch Fabric
As with the T S ri s platforms, the M320 FPCs contain from one to two complete PFE complexes. As was also the case with T Series, packets that ingress and egress on the same PFE complex (for example, PICs 0 and 1 or PICs 2 and 3 of a given FPC) do
fornot leave that PFE. The SIBs switch packets between PFEs across the crossbar switch fab ic as needed.
The M320 also makes use of a shared memory switch fabric for communications between and across FPCs and PFEs. In addition, inter-FPC communications require transit of the T Series-based crossbar switch fabric, which the system’s four SIBs form. Y u can configure an M320 with one to four active SIBs. Adding and activating more SIBs enables you to maintain line-rate forwarding performance for larger numbers of higher-bandwidth PICs (see the M320 Hardware Guide for a detailed performance breakdown). The M320 platform can operate with a SIB in standby mode for fault tolerance, but it does not have the space for a fifth SIB. Thus, if you configure an M320 to have a bandwidth requirement for four SIBs and you have a SIB failure, the router performance declines until you replace the affected SIB.
The M120 FPCs and Switch Fabric
Each M120 FPC contains a translator, a crossbar connection to the FEBs, power subsystem, and the physical PIC connectors. The translation component converts midplane signals to signals required by the types of supported PICs. The FEBs then, if necessary, switch the packet through the Control Board (CB) switch fabric to get to a different FEB.
Overview of JUNOS Platforms • Chapter 2–45
Troubleshooting JUNOS Platforms
Internet Processor II
The Internet Processor ASIC, which first shipped with the M40 in September 1998, heralded a breakthrough chnology that facilitated longest-match traffic forwarding for virtually all packet sizes at or very near line rate. Performance tests in the lab, test netwo ks, and on the Internet itself all demonstrated 40 Mpps of 40-byte packets with 80,000 p efixes in the routing table!
Building |
n this t adition, the Internet Processor II ASIC continues to deliver |
|
Reproduction |
best- -class functionality for network core and edge applications. While the Internet |
|
Pr cess |
II ASIC still delivers a 40 Mpps forwarding rate, the new ASIC adds rich |
packet pr |
cessing features that include firewall filtering, sampling, logging, counting, |
and enhanced load balancing. The Internet Processor II ASIC maintains high |
|
|
performance in the presence of value-added feature sets and enhanced services. |
for |
|
Not |
All T Series routers make use of the latest Internet Processor ASIC technologies. In |
fact, a T640 might contain as many as 16 Internet Processor II chips because on a |
|
T Series device, each FPC can contain from one to two complete PFE complexes, and |
|
each PFE receives service from its own Internet Processor II ASIC. |
|
On ABC chipset platforms, the C chip—actually the Cf chip (f is for filtering)—is the |
|
Internet Processor II chip. On LMNR chipset platforms, the R chip is the Internet |
|
Processor II chip. |
|
|
|
Chapter 2–46 • Overview of JUNOS Platforms