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Virtuoso Schematic Composer User Guide

Understanding Connectivity and Naming Conventions

where srcVectorExpression is the source and dstVectorExpression is the destination.

Naming Single and Multiple Bits Using Patchcords

Naming conventions for patchcords using vector expressions have exactly the same syntax as the vector expressions for wires with multiple bits. The number of bits in srcVectorExpression must equal the number of bits in dstVectorExpression.

In the following example, nets A and B are aliased together. Logically, each object that A is connected to is also connected to B, and the patchcord connects the first bit named in srcVectorExpression to the first bit named indstVectorExpression.

0=0

A

B

A B

In the following example, signal A is aliased to CNTR<2>, signal B is aliased to CNTR<1>, and signal C is aliased to CNTR<0>.

0:2 = 0:2

A,B,C

CNTR<2:0>

A CNTR<2>

B CNTR<1>

C CNTR<0>

October 2002

112

Product Version 5.0

Virtuoso Schematic Composer User Guide

Understanding Connectivity and Naming Conventions

In the following example, A<0> is aliased to B<3>, A<1> is aliased to B<2>, A<2> is aliased to B<1>, and A<3> is aliased to B<0>.

0:3 = 3:0

A<0:3>

B<0:3>

B<0>

A<0>

B<1>

A<1>

A<2>

 

 

 

 

 

 

 

B<2>

A<3>

 

 

 

 

 

 

 

B<3>

Naming Multiple Nets Using Patchcords

The following figure shows how to use patchcords to merge two buses.

 

 

 

0:7 = 0:7

DATA<7:0>

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

src

dst

( SYSBUS<15:8> )

 

SYSBUS<15:0>

8:15 = 0:7

ADDR<7:0>

( SYSBUS<7:0> )

src dst

The upper patchcord connects the eight-bit bus SYSBUS<15:8> to the eight-bit bus DATA<7:0>. The lower patchcord connects the eight-bit bus SYSBUS<7:0> to the eight-bit bus ADDR<7:0>.

The range of bits named in the lower patchcord using src_vector_expression <8:15> does not refer to the bits of SYSBUS. It refers to the order of the bits attached to the src pin of the patchcord. Therefore, according to the connection expression, bits 8 through 15 of bus SYSBUS<15:0> (corresponding to the bits named SYSBUS<7:0>) are connected to bit 0 through 7 of bus ADDR<7:0> (corresponding to the bits named ADDR<7:0>).

If you want to connect all the bits of the net to all the bits of the nets attached to the dst pin in the order they are attached to the src pin, omit the src vector expression and the equal sign ( = ) from the connection expression.

October 2002

113

Product Version 5.0

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