Virtuoso Schematic Composer User Guide

Traversing the Design Hierarchy and Creating a Design Configuration View

Exploring the Design Hierarchy

The following diagram shows an ALU and an ADDR symbol view instantiated in a schematic view.

schematic

Top-Level Design

Top-Level

Schematic

ALU instance

Virtuoso Schematic Composer User Guide

Traversing the Design Hierarchy and Creating a Design Configuration View

The following diagram shows the path (library, cell, and view name) for each view. You can traverse into any existing view of the cell that is referenced by an instance and whose view name has a corresponding view type in a registered tool.

64-bit microprocessor

ALU instance

Middle Level

myLib/ALU/symbol myLib/ALU/schematic myLib/ALU/vhdl myLib/ALU/functional

Lower Level

myLib/ADDR/symbol myLib/ADDR/schematic myLib/ADDR/behavioral

Top-Level Schematic View

The following illustration emulates descending from a top-level

I/O register schematic into a middle-level I/O latch schematic.

Virtuoso Schematic Composer User Guide

Traversing the Design Hierarchy and Creating a Design Configuration View

If you click the I3 IOlatch instance shown below, you descend into the schematic view (see next page) of an I/O latch for the instance named I3.

Middle-Level Schematic View

If you click the fflop1 component shown below, you descend from a middle-level I/O latch schematic into the lower-level fflop1 schematic (see next page).

Virtuoso Schematic Composer User Guide

Traversing the Design Hierarchy and Creating a Design Configuration View

Lower-Level Design Hierarchy

The following illustration shows the lowest level schematic of a design in the hierarchy of this particular design, the fflop1 schematic. The fflop1 schematic instantiates the primitive logic devices (or leaf nodes).

About the Configuration View of a Design Hierarchy

Setup and netlisting processes and simulations should be run from the configured view rather than the original schematic so that you can access the expansion information.