Virtuoso Schematic Composer User Guide

Checking Designs

AMS Checks

Description of AMS checks

The AMS CDBA-to-Verilog-AMS translator is a mixed-signal translator that supports the Verilog-AMS language standard. The purpose of the AMS checks is to give you feedback regarding CDBA-to-Verilog-AMS translation without having to actually generate a netlist. The checks must be enabled in order for them to run, but enabling netlisting is not necessary. By default, this feature is not enabled. For details, see the Cadence AMS Simulator User

Guide.

Checking a Design

You have several options for checking a design:

■Checking and Saving a Design on page 426

Virtuoso Schematic Composer User Guide

Checking Designs

■Checking the Current Cellview on page 428

■Checking a Design Hierarchy on page 429

■Checking a Design Hierarchy in the Configuration Context on page 430

■Checking Multisheet Schematics on page 431

■Checking a Label Attachment on page 432

■Cross-View Checking on page 433

Checking and Saving a Design

The Design – Check and Save command does the following:

■Checks either a schematic or a symbol cellview

■Extracts connectivity information from the graphics in the schematic

■Runs specified options using theschematic rules checker (SRC)

■Runs the cross-view checker (VIC)

■Saves the design

To check and save either a schematic or symbol, do the following:

1. Choose Design – Check and Save.

Virtuoso Schematic Composer User Guide

Checking Designs

After the check is completed, the Command Interpreter Window (CIW) shows the results of the check, and a dialog box appears.

icds - Log: /usr1/mnt1/mara/CDS.log

Schematic Check

Flashing highlighted markers in your schematic indicate the objects that have errors or warnings.

2.On the dialog box, click Close.

The Cadence® netlisters cannot generate the netlist until you check the design and, if necessary, correct any errors found during the check process.

You do not need to correct any warnings found during the check process, but you should review them before you attempt to generate a netlist.

If no errors exist, the system automatically saves your design.

Virtuoso Schematic Composer User Guide

Checking Designs

If errors exist, the system prompts you to save your cellview. You can change this default behavior by altering the value of the Check and Save Action on Error option on the

Schematic Check Options form.

Check and Save

3.Read the check results and reply to the form.

To find the errors, chooseCheck – Find Markers.

Checking the Current Cellview

The Check – Current Cellview command does the following:

■Checks either a schematic or a symbol cellview

■Extracts connectivity information from the graphics in a schematic

■Runs specified options using theschematic rules checker (SRC)

■Runs the cross-view checker (VIC) on views you can specify

Before checking a cellview, review the check options.

To check only the current cellview, do the following:

1.Choose Check – Current Cellview.

The software performs the check. After the check is completed, the CIW displays the results of the check, and a dialog box appears.

2.Read the check results and reply to the form.

3.Choose Check – Find Marker to view and resolve each error, if applicable.