Virtuoso Schematic Composer User Guide

Environment Variables

srcPinNetCollision

Specifies the severity of the SRC check for pin/net name collisions. Controls the check for pins that are connected to nets whose wire names do not match the pin. Setting schematic check options and rules are discussed in Chapter 10, “Checking Designs.”

srcShortedOutputs

Specifies the severity of the SRC shorted outputs check. Controls the check for component output or schematic input pins that are connected to any other component output or schematic input pins. Setting schematic check options and rules are discussed in Chapter 10, “Checking Designs.”

srcSolderOnCrossover

Specifies the severity of the SRC check for solder dots on crossovers (four or more wires at an intersection). Setting schematic check options and rules are discussed in Chapter 10, “Checking Designs.”

srcTermNameExpr

Specifies the regular expression to use when the SRC terminal name check is enabled.

Specifies the regular expression used in the terminal name check. Setting schematic check options and rules are discussed in Chapter 10, “Checking Designs.”

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srcTermNameSyntax

Specifies the severity of the SRC terminal name check. Controls name-syntax checking for net names. Setting schematic check options and rules are discussed in Chapter 10, “Checking Designs.”

Virtuoso Schematic Composer User Guide

Environment Variables

srcUnconnectedWires

Specifies the severity of the SRC unconnected wires check. Controls the check for wire segments whose endpoints do not physically connect to schematic or component pins, labels, or other wire segments. Setting schematic check options and rules are discussed in Chapter 10, “Checking Designs.”

srcVerilogSyntax

Specifies the severity of the SRC Verilog syntax name check. Controls the check for Verilog HDL syntax across all instance and signal names. This check verifies that names are valid Verilog HDL identifiers and are not Verilog HDL reserved words. Setting schematic check options and rules are discussed in Chapter 10, “Checking Designs.”

srcVHDLSyntax

Specifies the severity of the SRC VHDL syntax name check. Controls the check for VHDL syntax across all instance and signal names. This check verifies that names are valid VHDL

Virtuoso Schematic Composer User Guide

Environment Variables

identifiers and are not VHDL reserved words. Setting schematic check options and rules are discussed in Chapter 10, “Checking Designs.”

ssgSortPins

Specifies how the text-to-symbol generator sorts the symbol pins for the new symbol. For details, see Editor Options Form on page 780.

statusBanner

Specifies whether the status banner appears on all windows that contain schematic or symbol data. For details, see Changing Display Options on page 481.