Virtuoso Schematic Composer User Guide

10

Checking Designs

This chapter describes the procedures you use for checking your design.

Features of the Check Commands on page 416

Setting the Check Options on page 418

Setting User Preferences on page 418

Setting Schematic Rule Checks on page 420

Checking a Design on page 425

Checking and Saving a Design on page 426

Checking the Current Cellview on page 428

Checking a Design Hierarchy on page 429

Checking a Design Hierarchy in the Configuration Context on page 430

Checking Multisheet Schematics on page 431

Checking a Label Attachment on page 432

Cross-View Checking on page 433

Bypassing Checks on page 435

Bypassing Floating Pin Checks on page 435

Bypassing Unconnected Wire Checks on page 436

Resolving Check Errors on page 438

Finding Errors and Warnings in a Design on page 440

Mapping an Error Message to a Marker on page 441

Managing the Error Message List on page 441

Assigning an ignoreCheck Property on page 441

Virtuoso Schematic Composer User Guide

Checking Designs

Suppressing Message Displays on page 442

Deleting an ignoreCheck Property on page 442

Deleting All ignoreCheck Properties on page 442

Deleting Individual Markers on page 443

Deleting All Markers on page 443

Monitoring a Verilog or VHDL Simulation State on page 444

Using Cross Selection on page 445

Opening an SHM Database on page 445

Displaying the Simulation State of Wires and Pins on page 447

Setting a Time Value for Displaying Signal Results on page 448

Setting the Time Scale on page 449

Setting the Display Radius on page 450

Synchronizing with Simulation at Breakpoint on page 451

Closing the SHM Database on page 451

Features of the Check Commands

Before you can pass the design data to any other tools, you must check your design for connectivity, errors, and rule violations.

The Cadence® netlisters cannot generate the netlist until you check your design and, if necessary, correct any errors found during the check process.

You do not need to correct any warnings found during the check process, but you should review them before you attempt to generate a netlist.

The Virtuoso® Schematic Composer check commands are as follows:

Design – Check and Save

Check – Current Cellview

Check – Hierarchy

Check – Label Attachment

Virtuoso Schematic Composer User Guide

Checking Designs

Check – Cross-View Checker (VIC) (symbols only)

You can check schematics using the following commands.

The Design – Check and Save command runs most of the check commands simultaneously and

Checks either a schematic or a symbol cellview

Extracts connectivity information from the graphics in the schematic

Runs specified options using theschematic rules checker (SRC), such as logical and physical checks

Runs the cross-view checker (VIC) on views you can specify

Saves the design

The Check – Current Cellview command checks all the features that the Design – Check and Save command does, but it does not save the design.

The Check – Hierarchy command is identical to the Check – Current Cellview command, but it checks the entire hierarchy.

The Check – Label Attachment command

Shows the association between the labels and objects by drawing highlighted lines

Checks for unattached labels

The Check – Cross-View Checker (VIC) command uses a smaller criteria to check the interface of specified views.

Checks interface consistency between a list of specified views

Reports signals exported in one view but not in the other

Reports signals whose pins have different directions in the two views

Does not save the design