Virtuoso Schematic Composer User Guide

Checking Designs

Monitoring a Verilog or VHDL Simulation State

To debug a Cadence VHDL design, you can set breakpoints or traces on certain objects. You can use the Schematic Monitors commands only with an ongoing Verilog-XL or VHDL session or when accessing a previous simulator run stored with the simulation history manager (SHM). You can monitor or display any signal name as long as the signal name exists in the simulation data source SHM file.

The Schematic Monitors commands let you observe the simulation state directly on wires or pins that represent signals, giving you a sense that simulation is being performed directly on the design that you created.

This section describes the procedures for the following:

■Using Cross Selection on page 445

■Opening an SHM Database on page 445

■Displaying the Simulation State of Wires and Pins on page 447

■Setting a Time Value for Displaying Signal Results on page 448

■Setting the Time Scale on page 449

■Setting the Display Radius on page 450

■Synchronizing with Simulation at Breakpoint on page 451

■Closing the SHM Database on page 451

Virtuoso Schematic Composer User Guide

Checking Designs

Using Cross Selection

To enable cross selection to other Cadence applications via interprocess communication and to debug your design, do the following:

1.From the schematic editor, choose Options – Editor.

The Editor Options form appears.

2.Turn on Cross Selection.

3.Click OK.

Opening an SHM Database

You can open only one SHM database in each schematic editor window, but the SHM database can be opened by multiple schematic windows. You can open a new SHM database at any time. You must open an SHM database to display feedback from the Verilog-XL simulator or the Leapfrog® VHDL simulator in your schematic.

To connect a schematic window to an SHM database, do the following:

1. Choose Check – Schematic Monitors – Open Data.

Virtuoso Schematic Composer User Guide

Checking Designs

The Open Simulation Data form appears.

2.Choose a database.

3.Click OK.

A message in the CIW reports whether the SHM database was opened. The status banner is updated to show the SHM database name, the current simulation time, and the current design scope.

The Open Data command connects the schematic to an SHM database, which exists in one of two forms:

As a file created from a previous simulation

As an in-memory simulation history created by an active simulation

If you are accessing the currently active SHM database opened by the Verilog-XL simulator, any monitors you add are automatically probed. If monitors exist on your schematic, they display signal data from the new SHM database.

Virtuoso Schematic Composer User Guide

Checking Designs

Displaying the Simulation State of Wires and Pins

To display the simulation state of wires and pins, do the following:

1.Choose Check – Schematic Monitors – Add.

The Add Simulation Monitor form appears.

2.If you did not fill in theSignal Name field, the editor prompts you to click on a wire or pin.

Once you open a simulation database, the monitor displays the simulation state of the signal if it exists in the database. Add net names from wires, pins, or instances selected in the schematic. Type the signal names, separating each entry with a space.

If the name is not a valid name in the database, the signal is not monitored and a warning is issued.

If the signal name is made up of multiple bits, the state is displayed in bus format. The default bus radix is hexadecimal.

The following list shows each format and an example of how the schematic monitor appears.