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Файл:virtuoso schematic composer_5.0.pdf
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- •Contents
- •Preface
- •Related Documents
- •Typographic and Syntax Conventions
- •Getting Started
- •Starting the Schematic Composer
- •Using the Command Interpreter Window
- •Working with Designs
- •Opening a New Cellview
- •Opening an Existing Cellview
- •Using the Schematic Editor
- •Using the Symbol Editor
- •Making Designs Editable
- •Making Designs Read Only
- •Saving Your Edits
- •Closing Editor Windows
- •Quitting the Schematic Composer
- •Working with Libraries
- •Database Structure
- •Design Libraries
- •Reference Libraries
- •Library Browser
- •Using Menus and the Icon Bar
- •Using Pull-Down Menus
- •Using Pop-Up Menus
- •Using Object-Sensitive Menus (OSMs)
- •Using the Icon Bar
- •Working with Commands
- •Using Command Prompts
- •Canceling a Command
- •Undoing a Command
- •Redoing a Command
- •Displaying a Form
- •Using Form Buttons
- •Using Form Fields
- •Quick Reference Bindkey Charts
- •Quick Reference Bindkey Chart — Schematic Editor
- •Quick Reference Bindkey Chart — Symbol Editor
- •Quick Reference Bindkey Chart — Mouse Buttons
- •Quick Reference Bindkey Chart — General Bindkeys
- •Selecting Objects
- •Dynamic Highlighting
- •Using the Mouse to Select Objects
- •Extending the Selection Area of a Net
- •Selecting One Object
- •Selecting Multiple Objects
- •Selecting Parts of Objects
- •Selecting Wires
- •Selecting a Wire Name and Its Associated Wire Segments
- •Selecting a Pin and Its Associated Wire Segments
- •Selecting an Instance and Its Associated Wire Segments
- •Deselecting Objects
- •Working with Windows
- •Zooming
- •Panning
- •Redrawing a Window
- •Viewing the Same Cell in Two Windows
- •Saving View Area Settings in Memory
- •Restoring View Area Settings
- •Using the Library Browser
- •Accessing and Using the Library Browser
- •Changing the Browser Type Option
- •Using the Library Browser to Initialize Form Fields
- •Using the Component Browser
- •Accessing and Using the Component Browser
- •Changing the Browser Type Option to the Component Browser
- •Opening the Component Browser
- •Opening the Add Instance Form Instead of the Component Browser
- •Listing Components from Several Libraries
- •Changing the Component Browser Display
- •Connectivity with Objects
- •Instance Naming Conventions
- •System-Generated Names
- •Iterated Names
- •Wire Connections and Wire Naming Conventions
- •Wire-to-Wire Connections
- •Wire-to-Pin Connections
- •Wire-by-Name Connections
- •Wire-to-Iterated Instance Connections
- •Global Net Name Connections
- •Multiple-Bit Wire Connections
- •Tapping Multiple Bits of a Bundle
- •Tapping Multiple Bits of a Bus
- •Tapping Wire Intersections by Name
- •Designating Tap Size and Bit Order
- •System-Generated Net Names
- •Multiple-Bit Wire Naming Conventions
- •Using Vector Expressions in Multiple Signals
- •Evaluating Vector Expressions in Multiple-Bit Wire Names
- •Pin Connections and Pin Naming Conventions
- •Hierarchical Pin Names
- •Offsheet Pin Names
- •Bus Pin Names
- •Pin-to-Pin Connections
- •Tapping Pins
- •Naming Single and Multiple Bits Using Patchcords
- •Naming Multiple Nets Using Patchcords
- •Inherited Connections
- •Inherited Connections in a Hierarchy
- •The Syntax of an Inherited Net Expression
- •How Net Expressions Evaluate
- •Sample Net Expression Library
- •Inherited Connections Restrictions
- •Analyzing Net Expression Property Names and Evaluated Names
- •Summary of Naming Conventions
- •Creating Schematics
- •Getting Started with Schematics
- •Adding Instances
- •What Is an Instance?
- •Methods of Adding an Instance to Your Design
- •Adding Instances One by One
- •Adding Instances by Rows and Columns (an Array)
- •Adding Instances Using an Iterative Expression
- •Editing Instance Masters
- •Specifying the View to Use While Placing the Instance
- •Changing the View after an Instance Is Already Placed
- •Renumbering Instances
- •Adding Blocks
- •Adding Blocks
- •Adding Wires and Pins to Blocks
- •Changing the Block Pin Direction Rule
- •Changing the Direction or Name of a Single Block Pin
- •Changing the Names and Directions of Multiple Block Pins
- •Deleting Block Pins
- •Disabling Automatic Block Pin Creation
- •Adding Pins
- •Adding Schematic and Offsheet Pins
- •Showing Pin Connections
- •Adding Wires
- •Adding Narrow or Wide Wires
- •Using Wire Snap and Gravity Options
- •Using Wire Draw, Width, and Route Options
- •Using Wire Flight Lines Option
- •Routing Flight Lines
- •Manipulating Wires with Only the Mouse
- •Adding Wires to Schematic Instance Pins using SKILL
- •Adding Wire Names
- •Naming a Wire
- •Adding Wire Names
- •Adding Multiple Wire Names
- •Verifying Invisible Wire Names
- •Adding Net Expression Labels to Create an Inherited Connection
- •Adding a Net Expression Label to a Wire
- •Adding an Inherited Supply Symbol to a Wire
- •Editing a Net Expression Label
- •Changing the Net Expression Label Display
- •Deleting a Net Expression Label
- •Adding netSet Properties to Create an Inherited Connection
- •Adding a netSet Property to an Instance
- •Modifying a netSet Property
- •Deleting a netSet Property
- •Finding a Net Expression
- •Finding and Replacing a Net Expression
- •Finding Available Properties
- •Viewing the Evaluated Net Names
- •Viewing the Full List of all Hierarchical Paths
- •Checking the Net Expression
- •Adding Solder Dots
- •Adding Solder Dots
- •Deleting Solder Dots
- •Disabling Automatic Solder Dot Creation
- •Changing Solder Dot Size
- •Adding Notes
- •Adding Note Shapes
- •Adding Note Text
- •Importing an ASCII File for Note Text
- •Adding Patchcords
- •Adding Probes
- •Adding Probes to a Net, Pin, or Instance
- •Showing Probe Information
- •Removing Probes from a Net, Pin, or Instance
- •Removing All Probes
- •Saving Probes
- •Loading Probes
- •Creating a Multisheet Schematic
- •Browsing a List of Multisheets
- •Converting a Single-Sheet Schematic to a Multisheet Schematic
- •Adding New Sheets
- •Editing the Title Block
- •Editing the Sheet Border Size and Type
- •Adding Offsheet Pins to Multisheet Schematics
- •Understanding the Index Schematic
- •Going to and from the Index Schematic
- •Repositioning a Schematic within the Sheet Borders
- •Deleting Sheets
- •Reordering Sheets
- •Renumbering Sheets
- •Working with Cross-References
- •Understanding Cross-Reference Zones
- •Understanding Pin Cross-References
- •Understanding Cross-Reference Reports
- •Preparing to Cross-Reference
- •Displaying Cross-References
- •Zooming In to View All Cross-Referenced Pins One by One
- •Viewing Cross-Reference Reports
- •Editing a Cross-Reference Display
- •Controlling the Format String Syntax
- •Customizing the Format String Syntax
- •Customizing Multisheets
- •The Basic Procedure
- •Customizing the Types and Sizes of Sheet Borders
- •Customizing the Cross Reference Options Form
- •Drawing a Customized Sheet Border
- •Drawing a Sheet Border
- •Drawing Sheet Zones
- •Drawing Zone Labels
- •Adding the Sheet Zone Property
- •Adding a Title Block
- •Adding Title Block Values with Normal Labels
- •Adding Title Block Values with NLP and IL Labels
- •Verifying the Label Type
- •Adding Title Block Properties
- •Customizing Pin Cross-References
- •Presetting the Title Block Values
- •Creating Symbols
- •Setting Grid Options
- •Importing Symbols
- •Creating New Symbols
- •Drawing Lines
- •Drawing Rectangles
- •Drawing Polygons
- •Drawing Circles
- •Drawing Ellipses
- •Drawing Arcs
- •Adding Pins as Graphic Images
- •Adding Pins as Instances
- •Creating Custom Pins as Graphic Images
- •Duplicating Pin Figures in the Symbol Master
- •Making the Custom Pin Name Visible
- •Adding a Selection Box
- •Adding Labels
- •Adding a Normal Label
- •Adding an NLP Label
- •Adding an IL Label
- •Adding Note Text and Note Shapes
- •Adding a Net Expression Label
- •Setting the Symbol Origin
- •Creating Symbol Cellviews Using Generators
- •Automatically Creating Cellviews
- •Features of Creating Cellviews
- •Automatically Creating a Cellview from Another Cellview
- •Replacing an Existing Symbol Cellview
- •Modifying an Existing Symbol Cellview
- •Examples of Replacing and Modifying Pins on a Symbol
- •Automatically Creating a Cellview from a Pin List
- •Automatically Creating a Cellview from an Instance
- •Editing Symbol Generation Options
- •Adding, Changing, and Reordering Pin Names
- •Editing Pin Attributes
- •Loading and Saving a TSG Template File
- •Editing Symbol Attributes
- •Editing Symbol Labels
- •Creating a New Label
- •Deleting Labels
- •Modifying Label Attributes
- •Editing Properties
- •Creating a New Property
- •Deleting Properties
- •Modifying Property Attributes
- •Specifying Symbol Generator Pin Sorting
- •Editing Objects
- •Using Direct Manipulation
- •Direct Manipulation Operations
- •Turning Off Direct Manipulation
- •Undoing and Redoing an Edit
- •Changing the Undo Limit
- •Stretching
- •Stretching with the Schematic Editor
- •Stretching with the Symbol Editor
- •Stretching with Direct Manipulation
- •Stretching with Bindkeys
- •Copying
- •Copying Single Objects
- •Copying Arrays of Objects
- •Copying Across Cellviews
- •Copying with Direct Manipulation
- •Copying with Bindkeys
- •Moving
- •Moving Objects
- •Moving with Direct Manipulation
- •Moving with Bindkeys
- •Deleting
- •Deleting Preselected Objects
- •Deleting Postselected Objects
- •Deleting Sheet Borders
- •Rotating
- •Rotating Preselected Objects
- •Rotating Postselected Objects
- •Rotating with Direct Manipulation
- •Rotating with Bindkeys
- •Discarding Edits
- •Alternating Symbol Views
- •Changing the View of a Preselected Object
- •Changing the View of a Postselected Object
- •Toggling Objects
- •Toggling Pin Direction Options
- •Toggling Wire Draw Mode Options
- •Toggling Instance Symbol View Options
- •Saving the Current Label Display File
- •Loading the Current Label Display File
- •Attaching the Label Display File to the Library
- •Detaching the Label Display File from the Library
- •Setting the Simulation Data Directory
- •Editing Properties
- •Using Command Shortcuts
- •Search String Wildcards
- •Replacing Properties
- •Replacing String-Tagged Characters
- •Selecting Objects to Edit
- •Using Modal (Repeating) Commands
- •Selecting Objects by Filtering
- •Selecting Objects Automatically by Type
- •Selecting Objects by Property
- •Adding a Property Name to the Search List
- •Selecting Objects by Filtering
- •Object and Cellview Property Types and Values
- •Editing Object Properties
- •Applying Edits to Objects and Displaying Object Types
- •Adding Object Properties
- •Deleting Object Properties
- •Modifying Object Properties
- •Editing Instance and Block Properties
- •Editing Pin Properties
- •Designating the Order of Pins
- •Copying a Pin Order from Another Cellview
- •Resolving Pin Order Mismatch
- •Verifying Pin Order
- •Editing Pin Name Properties
- •Editing Wire Properties
- •Editing Wire Name Properties
- •Editing Instance Pin Properties on an Instance of a Block
- •Editing Label Properties
- •Resetting Invisible Labels
- •Editing netSet Properties
- •Editing Note Text Properties
- •Editing Note Shape Properties
- •Editing Symbol Shape Properties
- •Editing Symbol Pin Properties
- •Editing Symbol Label Properties
- •Editing Symbol Selection Box Properties
- •Passing Parameters in a Design
- •Editing Cellview Properties
- •Adding Cellview Properties
- •Deleting Cellview Properties
- •Modifying Cellview Properties
- •Editing VHDL Properties
- •Adding VHDL Properties
- •Deleting VHDL Properties
- •Modifying VHDL Properties
- •Setting the Tool Filter
- •About the Design Hierarchy
- •Exploring the Design Hierarchy
- •Top-Level Schematic View
- •Middle-Level Schematic View
- •Lower-Level Design Hierarchy
- •About the Hierarchy Editor
- •Traversing a Design Hierarchy
- •Descending Using the Descend Command
- •Editing an Instance in Place
- •Descending Using the View Name List
- •Setting the View Precedence Order
- •Returning Up the Design Hierarchy
- •Using OSMs to Traverse the Design Hierarchy
- •Using Bindkeys to Traverse the Design Hierarchy
- •Displaying the Current Hierarchical Scope
- •About the Hierarchy Editor within the Schematic Composer
- •Opening a Hierarchy Editor Menu within the Schematic Composer
- •Setting Instance Bindings
- •Building a New Inherited View List
- •Showing Views Found
- •Checking Designs
- •Features of the Check Commands
- •Setting the Check Options
- •Setting User Preferences
- •Setting Schematic Rule Checks
- •Checking a Design
- •Checking and Saving a Design
- •Checking the Current Cellview
- •Checking a Design Hierarchy
- •Checking Multisheet Schematics
- •Checking a Label Attachment
- •Cross-View Checking
- •Bypassing Checks
- •Bypassing Floating Pin Checks
- •Bypassing Unconnected Wire Checks
- •Resolving Check Errors
- •Finding Errors and Warnings in a Design
- •Mapping an Error Message to a Marker
- •Managing the Error Message List
- •Assigning an ignoreCheck Property
- •Suppressing Message Displays
- •Deleting an ignoreCheck Property
- •Deleting All ignoreCheck Properties
- •Deleting Individual Markers
- •Deleting All Markers
- •Monitoring a Verilog or VHDL Simulation State
- •Using Cross Selection
- •Opening an SHM Database
- •Displaying the Simulation State of Wires and Pins
- •Setting a Time Value for Displaying Signal Results
- •Setting the Time Scale
- •Setting the Display Radius
- •Synchronizing with Simulation at Breakpoint
- •Closing the SHM Database
- •Plotting Designs
- •Setting Up System Options to Plot
- •Setting Up Printer Options to Use Various Paper Sizes
- •Plotting a Design
- •Plotting a Library
- •Plotting a Cellview
- •Plotting Part of a Schematic
- •Plotting Without a Header Page for Every Session
- •Adding Notes to a Plot
- •Setting Plot Options
- •Plotting a Color Schematic in Black and White
- •Changing the Background Color of a Schematic Window
- •Using a Plot Template File
- •Creating a Plot Template File
- •Loading a Plot Template File
- •Creating a Default Plot Template File
- •Checking the Queue Status
- •Canceling a Plot Job
- •Setting Schematic Composer Options
- •Overview of Schematic Composer Options
- •Changing User Preferences
- •Minimizing Mouse Clicks
- •Changing the Default Display Setting for Command Option Forms
- •Saving the Current Window Setup
- •Restoring a Saved Window Setup
- •Viewing Bindkey Settings
- •Changing Browser and CIW Preferences
- •Customizing Editor Options
- •Canceling the Modal (Repeat) Command Option
- •Changing Display Options
- •Selecting Objects Using the Filter Option
- •Setting Plot Options
- •Setting Schematic Check Options and Rules
- •Setting the Tool Filter
- •Saving Form Field Default Settings
- •Loading Form Field Default Settings
- •Customizing the Schematic Composer
- •Customizing Pull-Down and Pop-Up Menus
- •Sample Menu File
- •Customizing Object-Sensitive Menus
- •Example of Customizing the Instance OSM
- •Customizing the Icon Bar
- •Positioning Icons and Turning Off Icon Names
- •Changing the Contents of the Icon Bar
- •Changing the Display of the Icon Bar
- •Understanding Initialization and Setup Files
- •Converting a Schematic from a 0.125 Grid to a 0.1 Grid
- •Customizing Bindkeys
- •Locating the schBindKeys.il Bindkey File
- •Locating Your Installation Directory
- •Loading Your Customized Bindkey File
- •Loading the Cadence-Supplied Bindkey File
- •Customizing Global Editor Variables for Form Fields
- •Schematic Editor Variables
- •Symbol Editor Variables
- •Symbol Generation (tsg) Variables
- •HDL (Verilog, SpectreHDL, and VerilogA) Variables
- •AMS Netlisting Variables
- •Block Pin Direction Rule Variable
- •Block Sample Sizes Variable
- •View Name Exclusion Variable
- •Schematic Pin Types Variable
- •Plot Template File Variable
- •Property Filter Variable
- •Schematic Rule Checker Variable
- •Properties for Find Variable
- •Multisheet Masters Variable
- •Simulation Probe Masters Variable
- •View Name Masters Variable
- •View Master Options Variable
- •Zone Formats Variable
- •Symbol Label Variables
- •Symbol Pin Masters Variable
- •Customizing Text-to-Symbol Generator (TSG) Variables for Form Fields
- •Pin Master Connections Variable
- •Symbol Pin Characteristics Variable
- •Template Masters Variables
- •Customizing HDL Variables for Form Fields
- •Edit After Error Variable
- •Update Symbol After Edit Variable
- •Cross View Check Variable
- •Cross View String Variable
- •Printing Variable
- •Verbose Variable
- •No Hierarchy Variable
- •Net to Port Variable
- •Environment Variables
- •Overview of Environment Variables
- •Schematic Editor Environment Variables File
- •Window Environment Variables
- •schDisplayDepth
- •schDrawAxesOn
- •schDynamicHilightOn
- •schGridMultiple
- •schGridSpacing
- •schGridType
- •schMaxDragFig
- •schPathType
- •schShowDirectConnects
- •schShowLabelOrigin
- •schSnapSpacing
- •schWindowBBox
- •symDisplayDepth
- •symDrawAxesOn
- •symDynamicHilightOn
- •symGridMultiple
- •symGridSpacing
- •symGridType
- •symMaxDragFig
- •symPathType
- •symShowDirectConnects
- •symShowLabelOrigin
- •symSnapSpacing
- •symWindowBBox
- •viewNameList
- •Schematic Environment Variables
- •autoDot
- •blockDirRules
- •broadcast
- •browserType
- •checkAlways
- •checkBeepOn
- •checkHierSave
- •checkSymTime
- •compBackTrace
- •condOp
- •createCvOptions
- •createInstResetCDF
- •createInstShowCDF
- •createLabelFontHeight
- •createLabelFontStyle
- •createLabelHorzOffset
- •createLabelHorzPosition
- •createLabelHorzRotation
- •createLabelJustify
- •createLabelOffsetMode
- •createLabelVertOffset
- •createLabelVertPosition
- •createLabelVertRotation
- •cvDisplay
- •defaultsFile
- •defWideWireWidth
- •descendSheet
- •descendTarget
- •dotOverlap
- •drawMode
- •drawModeRoute
- •echoToCIW
- •editPropShowCDF
- •editPropShowSystem
- •editPropShowUser
- •gravityOn
- •libList
- •markerSeverity
- •markerShowIgnore
- •markerZoom
- •maxLabelOffsetUU
- •minMarkerSize
- •modalCommands
- •netExprDisplay
- •netNameMethod
- •netNameRangeDescend
- •netNameSeparator
- •noteFontHeight
- •noteFontStyle
- •noteJustify
- •noteShape
- •noteShapeLineStyle
- •pinBackTrace
- •pinNameSeed
- •pinRefDuplicates
- •pinRefFormat
- •pinRefSorting
- •replSaveChanges
- •runSRC
- •runVIC
- •saveAction
- •schematicAreaPartialSelect
- •schematicSelectFilter
- •sensitiveMenu
- •shapeLineType
- •shapeLineWidth
- •simProbeFormat
- •simProbeType
- •snapEnabled
- •spanLib
- •srcConnByName
- •srcFloatingBIDIR
- •srcFloatingInput
- •srcFloatingIO
- •srcFloatingNets
- •srcFloatingOutput
- •srcInheritedConnCheck
- •srcInstNameExpr
- •srcInstNameSyntax
- •srcInstOverlap
- •srcInstOverlapValue
- •srcMaxLabelOffset
- •srcNameCollision
- •srcNetNameExpr
- •srcNetNameSyntax
- •srcNoOverrideNet
- •srcOffsheetConnCheck
- •srcPinNetCollision
- •srcShortedOutputs
- •srcSolderOnCrossover
- •srcTermNameExpr
- •srcTermNameSyntax
- •srcUnconnectedWires
- •srcVerilogSyntax
- •srcVHDLSyntax
- •ssgSortPins
- •statusBanner
- •statusBannerXY
- •stickyWireLabelRange
- •symbolAreaPartialSelect
- •symbolLabelChoiceText
- •symbolLabelFontHeight
- •symbolLabelFontStyle
- •symbolLabelJustify
- •symbolLabelType
- •symbolPinFlatten
- •symbolPinIncrCount
- •symbolPinLocate
- •symbolPinUsage
- •symbolSelectFilter
- •symbolShape
- •symbolShapeFillStyle
- •transToSheetType
- •tsgTemplateType
- •updateConn
- •vicExactPinMatch
- •vicInheritedPins
- •vicInheritedPinsMatch
- •vicSeverity
- •vicViewList
- •wireBackTrace
- •zoomOutButton
- •Text-to-Symbol Generator
- •Symbol Shape Generated by TSG
- •TSG Symbol Description File
- •TSG Template File
- •Clock and Negation Indicators
- •Backannotation
- •Simple File Example
- •Complex File Example
- •Extended File Example
- •TSG Symbol Description File Structure
- •Basic File Structure
- •Data Types
- •Using TSG Constructs
- •Input Pin
- •Output Pin
- •Executing TSG
- •TSG Processing Order
- •Creating Symbols Automatically from a Schematic
- •Terms and Conventions
- •Library Command File
- •Running the Symbol and Simulation Library Generator
- •Running the Symbol and Simulation Library Generator in the Cadence Graphic Environment
- •Running the Symbol and Simulation Library Generator in the Cadence Nongraphic Environment
- •Library Management Commands
- •lmCheckTerm
- •lmCheckView
- •lmCloseLib
- •lmDefCell
- •lmDefTermProp
- •lmDefViewProp
- •lmDeleteTermProp
- •lmDeleteViewProp
- •lmGetValue
- •lmLoadData
- •lmOpenLib
- •lmPrintLibTermProp
- •lmPrintLibViewProp
- •lmPrintTerm
- •lmPrintTermProp
- •lmPrintViewProp
- •lmReset
- •lmSimView
- •simRep
- •Variables That Control Command Execution
- •Properties That Modify Values
- •Sample Library Command File
- •Configuring and Using Kanji Notes
- •Overview
- •Installing the Required Files
- •Uncompressing the Files
- •Modifying the Schematic Editor Menu File
- •Setting the Environment Variable
- •Modifying the Data Registry File
- •Using Kanji Notes
- •Formats, Files, and Views
- •Adding a New Note
- •Generating a Symbol from an Existing File
- •Generating a Symbol from a New File
- •Editing an Existing Note
- •Limitations
- •Known Problems
- •schHiCreateKanjiSymbol
- •Form Descriptions
- •Add Block Form
- •Add Custom Pin Form
- •Add Generic Form – VHDL Properties
- •Add Instance Form
- •Add Kanji Note Form
- •Add Net Expression Form
- •Add New Property to Find Form
- •Add New Property to Replace Form
- •Add New Property for Search Form
- •Add Note Shape Form – Arc
- •Add Note Shape Form – Circle
- •Add Note Shape Form – Ellipse
- •Add Note Shape Form – Line
- •Add Note Shape Form – Polygon
- •Add Note Shape Form – Rectangle
- •Add Note Text Form
- •Add Pin Form – Schematic
- •Add Pin Form – Symbol
- •Add Property Form – Edit Object Properties
- •Add Selection Box Form
- •Add Simulation Monitor Form
- •Add Symbol Label Form
- •Add Symbol Shape Form – Arc
- •Add Symbol Shape Form – Circle
- •Add Symbol Shape Form – Ellipse
- •Add Symbol Shape Form – Line
- •Add Symbol Shape Form – Polygon
- •Add Symbol Shape Form – Rectangle
- •Add Wire Form
- •Add Wire Name Form
- •Build Inherited View List Form
- •Cellview From Cellview Form
- •Cellview From Instance Form
- •Cellview From Pin List Form
- •Cellviews with Evaluated Net Expression Name Form
- •Change Sheet Border Size Form
- •Check Hierarchy Form
- •Component Browser Form
- •Component Browser Preferences Form
- •Copy Form
- •Create Cellview Dialog Box – Replace or Modify
- •Create Schematic Form
- •Create Schematic Sheet Form
- •Cross Reference Options Form
- •Cross-View Checker Form
- •Delete All Markers Form
- •Delete Generic Form – VHDL Properties
- •Delete Property Form – Edit Object Properties
- •Delete Schematic Sheet Form
- •Descend Form – Descend Options
- •Descend Form – Iterated Instance
- •Descend Form – Multisheet
- •Descend Form – Noniterated Instance
- •Display Options Form
- •Edit Cellview Properties Form
- •Edit Component Display Form
- •Edit Object Properties Form – Basic
- •Edit Object Properties Form – Instance and Block
- •Edit Object Properties Form – Instance Pin
- •Edit Object Properties Form – Label
- •Edit Object Properties Form – Master Property
- •Edit Object Properties Form – Net Expression
- •Edit Object Properties Form – Note Shapes
- •Edit Object Properties Form – Note Text
- •Edit Object Properties Form – Other Object
- •Edit Object Properties Form – Pin
- •Edit Object Properties Form – Pin Name
- •Edit Object Properties Form – Selection Box
- •Edit Object Properties Form – Symbol Label
- •Edit Object Properties Form – Symbol Pin
- •Edit Object Properties Form – Symbol Shape
- •Edit Object Properties Form – Wire Name
- •Edit Object Properties Form – Wire Segment
- •Edit Pin Order Form
- •Edit Schematic Sheet Number Form
- •Editor Options Form
- •Find Marker Form
- •Go To Pin Form
- •Go To Sheet Form
- •Import Symbol Form
- •Left, Right, Top, Bottom Pin Attributes Form
- •Load Label Display Form
- •Load Schematic Defaults Form
- •Modify Generic Form – VHDL Properties
- •Modify Property Form – Edit Object Properties
- •Move Form
- •Net Expression Available Property Names Form
- •Net Expression Evaluated Names Form
- •Occurrence Paths to Evaluated Name Form
- •Open Simulation Data Form
- •Plot Options Form
- •Renumber Instances Form
- •Reset Invisible Labels Form
- •Rotate Form
- •Route Flight Line Form
- •Save Label Display Form
- •Save Schematic Defaults Form
- •Save Schematics with Errors Form
- •Schematic Check Options Form
- •Schematic Find and Symbol Find Forms
- •Schematic Replace and Symbol Replace Forms
- •Schematic Select All Form
- •Schematic Select By Property Form
- •Schematic Selection Filter Form
- •Schematic Title Block Properties Form
- •Set Instance Binding Form
- •Set Label Display Simulation Data Directory Form
- •Set Radix Form
- •Set Time Form
- •Setup Schematic Rules Checks Form
- •Show Label Form
- •Show Views Found Form
- •Stretch Form – Schematic Editor
- •Stretch Form – Symbol Editor
- •Submit Plot Form
- •Symbol Generation Options Form
- •Symbol Select All Form
- •Symbol Select By Property Form
- •Symbol Selection Filter Form
- •Synchronization Form
- •Time Scale Form
- •VHDL Properties Form
- •Glossary
Virtuoso Schematic Composer User Guide
Text-to-Symbol Generator
A template file helps avoid unnecessarily large TSG description files. You can specify TSG constructs shared by a large group of symbols within a single template file. This allows you to create TSG symbol description files that contain only constructs specific to a particular symbol.
®
The first time you use TSG during a Virtuoso schematic composer session, a default template file is automatically loaded. This default template file is always used unless you specify an optional template file argument in the call to execute TSG, as described later.
Settings specified within the currently active template file will apply to all symbols generated by TSG unless overridden by constructs specified within the TSG symbol description file. You can find available template filenames within thetsgTemplateMasters list, which is defined in the schConfig.il file. The default template file that is chosen depends on the initial setting of the tsgTemplateType environment variable.
Clock and Negation Indicators
To alter the appearance of certain pins, you can specify special pin graphics; for example:
■To identify a clock pin, you can draw a clock indicator (a small triangle) at the beginning of the pin wire
■For a negative logic pin, you can draw a negation indicator (a bubble) at the beginning of the pin wire
The example TSG files and associated figures illustrate some of these capabilities. Refer to the PinGraphicSpec construct and the wireLength and pinConnector symbol parameters.
Backannotation
After laying out parts for printed circuit boards (PCB), you often need to backannotate to schematics or PCB maps parameters, such as pin numbers and reference designators of symbol instances.
You can include constructs in the TSG symbol description file that specify the properties and parameters required to support the backannotation operation.
Simple File Example
The simplest TSG symbol description for an SN74LS181 symbol has the following format:
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defcell("tsgfig1"
input(A0 A1 A2 A3 B0 B1 B2 B3 Cn Set Reset)
output(F0 F1 F2 F3 C)
defsymbol(symbolProps( partName = "TSGFIG1"))
)
The following example shows a symbol generated from the TSG symbol description file shown above.
Complex File Example
A more elaborate version of a TSG symbol description file for an SN74LS181 symbol has the following format. This symbol was generated using the PCB package.tsg template file as an argument to the tsg command:
tsg( "exampleLib" "~/tsgFiles/fig2.tsg" prependInstallPath("samples/symbolGen/package.tsg") )
defcell("tsgfig2"
input( A0 A1 A2 A3 B0 B1 B2 B3 Cn Set Reset) output( F0 F1 F2 F3 C)
defsymbol(
symbolProps(
vendorName = DEMO partName = "TSGFIG2" refDes = U2 )
pinNumSpec(
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A0:1 |
A1:2 |
A2:3 |
A3:4 |
B0:18 |
B1:17 |
B2:16 |
F0:7 |
F1:8 |
F2:9 |
F3:10 |
C:11 ) |
pinLocSpec(
topPins( Set) bottomPins( Reset) )
pinGraphicSpec(
A0:actLo |
A1:actLo |
A2:actLo |
A3:actLo |
B0:actLo |
B1:actLo |
B2:actLo |
B3:actLo |
Cn:clock |
Set:actLo |
Reset:actLo |
F0:actLo |
F1:actLo |
F2:actLo |
F3:actLo |
C:actHi ) |
)
)
The following example shows a symbol generated from the TSG symbol description file shown above.
Extended File Example
The following example demonstrates many of the available TSG constructs.
defcell("count4" input("clock" "reset")
output("a0" "a1" "a2" "a3")
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defsymbol( |
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symbolProps( |
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partName |
= "count4" ; cellview prop with valueType=string |
||
pinNum |
= (4 (0 24)) |
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timeVal |
= time("Jan 1 12:00:00 1993") |
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color |
= ("red" ("red" "green" "blue")) |
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defTermProp( |
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input Iih = 1.24 ) ; all pins get property “a”. |
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defTermProp( |
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all b=6 ) |
; all pins get property "b". |
symbolParam( |
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wireSpacing = 0.125000 wireLength = 0.250000 vSideLength = 0.000000 hSideLength = 0.000000 origin = topLeftPin pinConnector = "block"
)
symbolLabels(
defLabel( name("[@partName]")
location( "(xleft + xright)/2:(ytop + ybottom)*3/4") labelType(NLPLabel)
layer(device)
purpose(label)
)
defLabel( name("[@instanceName]") location( "xleft:(ytop + ybottom)/2") labelType(NLPLabel) justification(upperLeft) layer(instance)
purpose(label)
apply(cellview)
fontHeight(0.1)
)
defLabel( name("{pinName}") location( "1.15*stubLength:0") justification(centerLeft) apply(left)
)
defLabel( name("[@p_{pinName}]") location( "-stubLength/2:0.03125") labelType(NLPLabel)
layer(pin)
purpose(annotate)
apply(right)
)
)
pinNumSpec( "a0":16 "a1":17 "a2":18 ) pinGraphicSpec( "reset":ieeeActLo "clock":clock )
)
)
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