Virtuoso Schematic Composer User Guide

Glossary

A

array

An ordered arrangement of instances in rows and columns with uniform spacing.

attribute

A mandatory characteristic of a design object or cellview, such as the wire width attribute, that you can change but cannot delete. It is a permanent and predefined part of the database. For example, a wire requires a beginning coordinate and an ending coordinate, and an instance requires an instance name.

In contrast, properties are optional; attributes are not. Properties can be added, changed, or deleted. Attributes can be added or changed, but they cannot be deleted. See also property.

B

backannotation

The process of passing information generated outside Virtuoso® schematic composer and storing the information in Virtuoso® schematic composer.

block

A generic instance that represents lower-level design data.

browser

A window used for displaying the names of libraries, cellviews, views, or components for a form field. Examples of browsers are the Component Browser and the Library Browser.

Virtuoso Schematic Composer User Guide

Glossary

You can use the Component Browser to display multiple libraries and their available components at the same time; to display a hierarchical list of components instead of an alphabetical list; to go directly to a specific component without scrolling.

You can use the Library Browser to view information about the libraries you have specified in yourcds.lib file.

bundle

A collection of signals with different names. A bundle is represented by names separated by a comma; for example, A,B,Data<0:15>. See also wire.

bus

A collection of signals sharing a common base name. A bus is represented by this base name followed with a vector expression; for example, A<0:7>. See also wire.

bus tapping

Tapping bits of a bus or bundle gives the tapping wire segments names that are members of the base bus or bundle. For example, in the following illustration, all names on the right column are taps from the bundle S,R,Q<0:15>.

Q<5:3>

S,R,Q<0:15>

S,R

Q<0:7>

S

Q<0>

C

CDBA

The database mechanism or application programming interface (API) used by Virtuoso® schematic composer for accessing design databases. It is traversed by netlisters like prflatten. CDBA stands for C-level Database Access.

Virtuoso Schematic Composer User Guide

Glossary

cell

A component of a design; a collection of different aspects (representations) of component implementations, such as schematic or symbol representations. A design object consisting of a set of views that can be stored and referenced independently.

An inverter and a buffer are examples of a small cell. A decoder register, arithmetic logic unit (ALU), memories, complete chips, and printed circuit boards are examples of large cells.

cellview

A specific representation (view) of a cell. A particular representation of a particular component, such as a schematic symbol of a NAND gate.

Cellviews are classified by their view type. Each cellview has a view name.

Command Interpreter Window (CIW)

The window that launches any Cadence Design Framework II application. The CIW logs your design session and reports messages.

connectivity

The way in which components and pins are linked together in an unambiguous manner. The connectivity in a schematic is represented by wires linking the component pins to other component pins. Connectivity can also be represented by pins of the common name (connection by name). The connectivity of a cellview is created by either the

Design – Check and Save command or the Check – Current Cellview command.

cross selection

The process of selecting an object in one view to automatically select the corresponding object in another Cadence application. For example, selecting an instance in a schematic cellview to cross highlight the corresponding instance in the Hierarchy Editor.

D

delay

The time interval between the manifestation of a signal at one point and the manifestation or detection of the same signal at another point.

delay path

An ordered series of instance-pin pairs that forms a connected signal path.

direct manipulation

Clicking on an object and then dragging the mouse to quickly stretch, move, and copy objects.

Virtuoso Schematic Composer User Guide

Glossary

E

editor, schematic

The interactive editor in which you can create schematic cellviews and edit objects that represent parts of the design, such as components and pins, and wires that establish connectivity between them.

editor, symbol

The interactive editor in which you can create and edit schematic symbol cellviews using labels, pins, shapes, notes, and a selection box.

Enter Function

A class of functions that gather data from the user interactively. Schematic composer uses enter functions to build the interactive commands that require performing actions with the mouse.

F

font

The style and size of type, in Virtuoso® schematic composer, of the label text. The choices are euroStyle, gothic, math, roman, scr ipt, stick, swedish, and

milSpec. The math font displays mathematical and Greek symbols. The swedish font displays Swedish language characters.

G

gate

Symbol object for combinational logic; for example, AND gates and OR gates.

gate array

Gates placed in a prefabricated matrix where you provide the design for the interconnect. Gate array designs are cheaper to manufacture because only the interconnects have to be custom made.

ge

The graphics editor component of DFII that supports both Virtuoso® schematic composer and Virtuoso® layout editor. It supplies a variety of functionality including display, selection, and hierarchical signal probing.

Virtuoso Schematic Composer User Guide

Glossary

global signal or global net

A signal that is connected by name across all levels of a design hierarchy without using pins. In Cadence Database Access (CDBA), a global signal is a signal that has the isGlobal attribute set to true. In schematics, a global signal is determined by name; if the signal name ends with an exclamation point ( ! ), it is considered global. A signal that is explicitly passed everywhere in a design is not considered global. A global signal connects to other signals with the same name elsewhere in the hierarchy without requiring an explicit connection through the hierarchy. See inherited connections.

H

hierarchical design

Division of portions of large designs into manageable views that can be created, represented symbolically, edited, and called by or connected to other such views in a design, optimizing gate production through tool speed and distribution of work load across a design organization.

I

ilInst

The ilInst SKILL variable provides self-reference to an instance during graphic display of the cellview containing the instance. The typical usage is for IL labels, such as labels that evaluate a SKILL expression and display the results. For example, to display the value of an instance property, you create an IL label with the value ilInst~>propertyName. The expression ilInst~>propertyName is evaluated for all instances of the cell and the resulting values are displayed in the graphic editor.

The ilInst SKILL variable is only evaluated for the instances in the top display level.

That is, only the instances in the schematic can have the ilInst SKILL variable value defined. If, for example, you are instantiating schematics in schematics in schematics, ilInst can only be determined for the instances in the top schematics, and all subinstances are evaluated with reference to the subschematic in which they are instantiated.

lLLabel

IL labels are expressions that are evaluated by the SKILL language to determine the value. When you place an instance in your schematic, the system evaluates the SKILL expression and displays the resulting value. For example, the system displays the IL label ilInst~>name in the symbol editor, but displays a value – for example, I3 – in the schematic editor. Other types of labels are normal and NLPLabel.

Virtuoso Schematic Composer User Guide

Glossary

inherited connections

A facility for specifying global signals that may be overridden for a particular branch of the hierarchy. Net expression labels are used to specify the default signal and the property name which the global signal looks for. netSet properties can be placed on instances to override the default signal for a branch of the hierarchy.

inherited net expression

A use of the NLP expression to support declaring an inherited connection.

instance

An instantiation of a lib cell symbol. It is a database object that represents a master cellview. You can have several instances of the same cellview in a design.

instance iteration

A compact way of representing repeated instances of a symbol in your schematic. Particularly useful in bus-type or data-flow architectures that have identical structures to handle each bit on the bus.

interpreted label

Represents the group of ILLabel and NLPLabel because their values are always derived.

J

justification

Position of the label’s origin with respect to the label. The cursor is always attached to the origin point. The choices are upperLeft, upperCenter, upperRight,

centerLeft, centerCenter, centerRight, lowerLeft, lowerCenter, and

lowerRight. For example, if you specify lowerCenter, the cursor is centered below the label.

M

member net

A bit of a net. For example, if a net had the name X,vdd!,Z, then the net has three members named X, vdd!, and Z.

member terminal

A bit of a terminal. For example, if a terminal had the name X,vdd!,Z, then the terminal has three members named X, vdd!, and Z.

Virtuoso Schematic Composer User Guide

Glossary

multisheet

The use of several pages to represent a schematic, connected by pins. You use two levels of hierarchy, the index and sheet levels. This partition improves readability and produces better plot output.

multisheet, index

A schematic representation that is given the instance of all the sheets. This schematic is not intended to be edited manually.

multisheet, pin

Connects nets between sheets in a multisheet schematic. A pin can connect a single signal or multiple signals (buses) of a terminal.

multisheet, sheet

A schematic containing the logical description of a sheet that can be connected to other sheets with offsheet pins.

N

net

A database object that describes one or more signals. Logical implementation of a single signal or a group of signals that implements the connections to instance pins and pins of the cellview containing the net.

net expression

A use of the NLP expression to support declaring an inherited connection.

net expression label

The object for displaying the value of net expressions to the user.

net, global

Used to establish connectivity between nets in different levels of the hierarchy. Indicated by an exclamation mark added to the end of the name; for example, vdd!

NLP

Netlist property. NLP expressions, besides being used for netlisting, are also used to display evaluated property values. The syntax of NLP expressions can be used to support inherited net expressions.

Virtuoso Schematic Composer User Guide

Glossary

NLPLabel

A CDBA label type. Other types of labels are Normal and ILLabel. Labels that are of

NLPLabel type undergo special NLP evaluation. In general, NLP expressions define a property name to look for, where to look for the property, a format string used to substitute a found property value, and a default value to use if the property is not found. The at sign ( @ ) in the net expression label specifies the beginning of a property substitution expression, as [@instanceName]. It specifies how NLP label expressions are interpreted.

O

OSS

Open Simulation System. The functionality provided within OSS is utilized by many applications and customers for writing netlist interfaces to a variety of tools.

P

patchcord

A special connection symbol used to establish aliases between the signals of two different nets.

Unlike tap names, where you extract bits of a single net, you can use patchcords to copy one net to another. You can also use the patchcord to map bits from one net to different bits of another net.

pin

Represents the connection point for a single signal or multiple signals of the terminal.

pin, offsheet

Connects nets between sheets in a multisheet schematic. A pin can connect a single signal or multiple signals (buses) of a terminal.

placed master

The master cellview of the instance placed in a schematic. Usually, this is the symbol cellview. The instance in a schematic references the symbol.

property

A characteristic of a design object or cellview that affects the object and can be edited or deleted. Properties can be mandatory or optional. See also attribute.

Virtuoso Schematic Composer User Guide

Glossary

S

signal

A database object that represents a scalar, logical entity that connects one or more member instance terminals. A scalar net is equivalent to a signal.

Ties together all the nets that implement the signal. Can belong to a number of different nets. See also wire.

solder dot

Small filled-in circle used to identify connections between intersecting wires that are part of the same net.

switched master

When a design hierarchy is traversed, the symbol views instantiated as the placed master do not define the next level of the design. The placed view must be switched to another view of the same cell that contains more detail, for example, the layout or schematic views. The view that defines the result of hiearchical descend is the switched master.

T

technology file

A file that defines all the physical information required for a design. It defines information such as layers, physical design rules for compaction, and devices.

terminal

Logical counterpart of the pin that lets you connect from the next higher level of hierarchy to the net associated with the pin.

A database object that makes a net available for connection on instances of a given cellview.

V

view, schematic

Contains connectivity data and graphics that describe the logical views of a design.

Virtuoso Schematic Composer User Guide

Glossary

view, symbol

Graphic representation of the interface between the current level of hierarchy to the level below the symbol that is instantiated.

Symbol view

Schematic

view

Mask layout view

W

wire

A line that connects a pin and an instance to represent a net in a schematic. When you draw a wire between a pin and an instance, you create a net.

wire name

Designates the name of a net and signals represented by the wire.