Virtuoso Schematic Composer User Guide

Customizing the Schematic Composer

Template Masters Variables

tsgTemplateMasters

This IL structure contains a list of tsgType/tsgTemplateFile pairs. Each tsgTemplateFile contains a different set of defaults for use by TSG when creating symbols. The environment variable tsgTemplateType is associated with the initialization of the default tsgType.

tsgTemplateMasters = list(

list("digital" (prependInstallPath "samples/symbolGen/ default.tsg"))

list("analog” (prependInstallPath "samples/symbolGen/ analog.tag"))

list("PCB" (prependInstallPath "samples/symbolGen/ package.tsg"))

list("metric" (prependInstallPath "samples/symbolGen/ metric.tsg"))

)

You can customize the four default TSG template masters in the schConfig.il file, or you can create a new TSG template file that contains the current settings within the Symbol Generation options form.

To customize template master variables, do the following:

1.Open the schConfig.il file and search for thetsgTemplateMasters section.

2.Edit the template masters or copy one of the four template masters to use as a new template master.

The system uses the tsgTemplateType environment variable to determine which template file to use.

Customizing HDL Variables for Form Fields

Use the following variables for customizing form fields for HDL.

Edit After Error Variable

schHdlEditAfterError

Edits Verilog®-A or Verilog simulator descriptions again if a syntax error is found.

Examples

schHdlEditAfterError = nil schHdlEditAfterError = t

Virtuoso Schematic Composer User Guide

Customizing the Schematic Composer

Update Symbol After Edit Variable

schHdlUpdateSymbolAfterEdit

After you edit Verilog or Verilog-A text, the symbol associated with the cell is conditionally updated to match the pinout of the Verilog module. A flag that controls the updating of the symbol can be set to one of three values:

t : If required, update symbol after editing nil : Don’t update symbol after editing

"query" : Display dialog box, asking if you want symbol

Example

updatedschHdlUpdateSymbolAfterEdit = "query"

Cross View Check Variable

schHdlCrossViewCheck

Enables or disables cross-view checking after editing Verilog or Spectre® HDL. If turned on, cross-view checks are performed after editing Verilog or Spectre HDL.

Examples

schHdlCrossViewCheck = nil ; disable xview checks schHdlCrossViewCheck = t

Cross View String Variable

schHdlCrossViewString

If cross-view checking is turned on, all views are checked against the edited view. Use schHdlCrossViewString to specify a particular set of views to check. A nil value or

“” checks all views.

Examples

schHdlCrossViewString = "schematic symbol" schHdlCrossViewString = ""

Printing Variable

schHdlPrintCommand

The UNIX command used by the Design – Print menu item in the Verilog or Spectre HDL view window.

Virtuoso Schematic Composer User Guide

Customizing the Schematic Composer

Examples

schHdlPrintCommand = "lw -Plw1" schHdlPrintCommand = "lpr"

Verbose Variable

schHdlVerbose

Prints out diagnostic messages while the Verilog text is parsed and processed. This is a tristate flag:

t | nil | "all"

If hdlVerbose is set to all, a detailed description of the pseudoschematic is displayed in the CIW. The output can be quite lengthy.

Examples

schHdlVerbose = t schHdlVerbose = nil

No Hierarchy Variable

schHdlNoHierarchy

This flag turns the mixed text-graphics feature on and off. If the flag is set, instance information is ignored when the Verilog text is postprocessed. Verilog descriptions edited when this flag is set can be used only as leaf cells in a netlist.

Examples

schHdlNoHierarchy = t schHdlNoHierarchy = nil

Net to Port Variable

schHdlNetToInputPort

schHdlNetToInoutPort

Port direction for instantiated Verilog modules is inferred by their connection to primary I/O or internal registers. The following variables map the inferred port type (input or inout) to the connecting net type. All other nets are assumed to be connected to instance output ports. The valid values in the list are reg, time, integer, real, expression, net, and unknown.

Virtuoso Schematic Composer User Guide

Customizing the Schematic Composer

Examples

schHdlNetToInoutPort = ‘("net")

Default File

schHdlNetToInputPort = list(reg time integer real expression) schHdlNetToInoutPort = nil

Customizing the Plot Configuration

Most of the choices for the cyclic fields on the Plot Options form are set in the display resource file, called thecdsplotinit file, which you can edit. This file is the foundation plotter model data base for Cadence Design Systems plot software. This file builds site specific

.cdsplotinit files.

You must create a site-specific version of the cdsplotinit file and locate it in your_install_dir/tools/plot, your working directory, or your home directory.

A read-only version of the cdsplotinit file is located inyour_install_dir/tools/ plot/etc/cdsplotinit. You can copy this file to your working directory or your home directory and then edit it. A sample .cdsplotinit file is available in your_install_dir/tools/plot/samples/cdsplotinit.sample.

You can edit the following specifications:

■Type and name of plotter

■Paper size

■Page orientation

■Page size

■Resolution