Virtuoso Schematic Composer User Guide

Form Descriptions

Setup Schematic Rules Checks Form

Packaged Checks automatically sets the severity levels for the following predefined checks.

These checks are defined by theschSRCPackagedChecks environment variable.

None sets the logical, physical, and name check severity levels to the default values.

Normal sets the logical, physical, and name check severity levels to either ignored or warning.

Logical Only sets all logical check severity levels to warning. Physical and name check severity levels are set to ignored.

Physical Only sets all physical check severity levels to warning. Logical and name checks are set to ignored.

VHDL sets logical, physical, and name check severity levels to preassigned values.

VHDL syntax checks are set to error.

Verilog sets logical, physical, and name check severity levels to preassigned values. Verilog syntax checks are set to error.

Logical checks the high-level connectivity data.

Floating Nets checks for wires that are neither physically nor logically connected to a schematic or instance pin. Ignores wires that are connected by name to a schematic or instance pin.

To minimize the number of messages when you set the severity levels for this check to warning or error, you should set the Unconnected Wires check in the Physical

Checks section of the form to ignored.

Floating Input Pins checks for component input pins and schematic output pins that are not connected to component output pins, schematic input pins, or schematic I/O pins.

Floating Output Pins checks for component output pins and schematic input pins that are not connected to component input pins, schematic output pins, or schematic I/O pins.

Floating I/O Pins checks for component or schematic input/output pins whose signals are not connected to component output pins, schematic input pins, or any other schematic I/O pins.

Floating Switch Pins checks for component or schematic bidirectional pins whose signals are not connected to component output pins, schematic input pins, or any other schematic I/O pins.

Shorted Output Pins checks for component output or schematic input pins that are connected to any other component output or schematic input pins.

Virtuoso Schematic Composer User Guide

Form Descriptions

Offsheet Connectors checks for offsheet connectors that appear on only one sheet in a multisheet design. Also checks whether a net is used locally in more than one sheet but is not connected across the sheets with an offsheet connector.

Physical checks for unconnected wires, offset labels, and overlapping instances.

Unconnected Wires checks for wire segments whose end points do not physically connect to

A schematic pin

A component pin

A label

Another wire segment

This check is a physical check, not a logical or connectivity check.

To minimize the number of messages when you set the severity levels for this check to warning or error, you should set the Floating Nets check in the Logical Checks section of the form to ignored.

Solder On CrossOver checks for solder connections placed on wire crossovers.

Overlapping Instances checks for instances that overlap other instances.

Percent Overlap Allowed specifies a value that defines the degree to which two instances can overlap each other. The value represents a percentage of the bounding box for the larger instance.

Maximum Label Offset checks for unglued labels beyond a specified distance from a wire (see Maximum Offset From Wire option). When the checker finds unglued labels within this specified distance, the checker automatically glues the labels to the appropriate wires if the severity level is set to warning or error.

Maximum Offset From Wire specifies the distance that an unglued label can be located from a wire. When the checker finds unglued labels beyond the specified distance, the checker marks the unglued label (see Maximum Label Offset option).

Name checks for syntax and collisions.

Connection By Name checks whether a signal exists in more than one physically disjointed group of wires or pins. You might have inadvertently connected objects when using a name that was already used elsewhere in the schematic. For example, if a schematic contains a pin name “A” and you name a wire in the schematic “A”, the pin and the objects connected to the wire are logically connected.

Virtuoso Schematic Composer User Guide

Form Descriptions

Instance/Net Name Collision checks whether a signal name collides with an instance name. For example, the schematic rules checker will flag an instance named “x” and a net named “x” because the names are identical. This option is especially useful for ensuring Verilog HDL and VHDL consistency.

Pin/Net Name Collision checks whether a pin name differs from a net name. For example, the schematic rules checker will flag a pin named “x” and a net named “y” because the names differ. It flags the condition of a pin name connected to a wire with a different net name; it does not flag connection by name.

Verilog HDL Syntax checks Verilog HDL syntax for instance and signal names in a schematic cellview. The checker flags signal names or instance names when they collide with Verilog HDL reserved words or when they are not valid Verilog HDL identifiers.

VHDL Syntax performs VHDL syntax checking on instance and signal names in a schematic cellview. The schematic rules checker flags signal names or instance names when they collide with VHDL reserved words or when they are not valid VHDL identifiers.

Instance Name Syntax controls name syntax checking for instances.

Instance Name Expression specifies the regular expression the checker uses in instance name syntax checks. This field is enabled only when the Instance Name Syntax check is set to warning or error.

Pin Name Syntax controls name syntax checking for pins.

Pin Name Expression specifies the regular expression the checker uses in pin name syntax checks. This field is enabled only when thePin Name Syntax field is set to warning or error.

Net Name Syntax controls name syntax checking for nets.

Net Name Expression specifies the regular expression the checker uses in net name syntax checks. This field is enabled only when theNet Name Syntax field is set to warning or error.

Inherited Connection checks existing or missing inherited connections.

Inherited Pin/Net Connections checks whether any inherited pin or net connections exist in the schematic.

Missing Override Nets checks for net names that have been specified by inherited connection override properties. If the net name is not found, the appropriate severity marker will be placed on the instance where the netSet property is defined.

AMS checks Analog Mixed Signal netlisting checks.

Run AMS Checks

Virtuoso Schematic Composer User Guide

Form Descriptions

yes runs AMS checks.

no (default) does not run AMS checks.

Verilog AMS Checks supports the Verilog-AMS language and runs netlisting checks.

Illegal Identifiers checks all identifiers in the cellview for adherence to Verilog-

AMS naming restrictions (which allows mixed-case identifiers). This includes syntax checking and checks for reserved words. Verilog-AMS allows mixed-case identifiers.

Name Collisions checks all identifiers in the cellview for adherence to Verilog-AMS scoping rules.

Conflicting Bus Ranges checks all buses in the cellview for consistent bus range direction.

Sparse Buses checks all buses in the cellview for use of each bit within the bus range.