Chapter 10 High-Precision Timing (Counters/Timers)

TIO-ASIC, DAQ-STC, and Am9513

When generating a pulse or pulse train with the TIO-ASIC, DAQ-STC, or Am9513 chip, you can define the polarity of the signal as positive or negative. Figure 10-4 shows these pulse polarities. Notice that for a signal with a positive polarity, the initial state is low, while a signal with a negative polarity has a high initial state.

Figure 10-4. Positive and Negative Pulse Polarity

Each counter-generated pulse consists of two phases. If the counter is configured to output a signal with positive polarity and toggled output, as shown in the following diagram, the period of time from when the counter starts counting to the first rising edge is called phase 1. The time between the rising and the following falling edge is called phase 2. If you configure the counter to generate a continuous pulse train, the counter repeats this process many times as shown on the bottom line of Figure 10-5.

counter starts

Figure 10-5. Pulses Created with Positive Polarity and Toggled Output

8253/54

When generating a pulse with the 8253/54 chip, the hardware limits you to a negative polarity pulse, as shown in Figure 10-4. The period of time from when the counter starts counting to the falling edge is called phase 1. The time between the falling and following rising edge is called phase 2. Figure 10-6 shows these phases for a single negative-polarity pulse.