Chapter 10 High-Precision Timing (Counters/Timers)

To create a positive-polarity pulse, you can connect your negative-polarity pulse to an external 7404 inverter chip.

Figure 10-6. Phases of a Single Negative Polarity Pulse

When generating a pulse train with the 8253/54 chip, the hardware limits you to positive polarity pulses. Furthermore, the value loaded in the count register is divided equally to create phase 1 and phase 2. This means you will always get a 0.5 duty cycle if the count register is loaded with an even number. If you load the count register with an odd number, phase 1 will be longer than phase 2 by one cycle of the counter CLK signal.

Now that you know the terms involving generating a single square pulse or a pulse train, you can learn about the LabVIEW VIs and the physical connections needed to implement your application.

Generating a Single Square Pulse

You can use a single pulse to trigger analog acquisition or to gate another counter operation. You also can use a single pulse to stimulate a device or circuit for which you need to acquire and test the response.

TIO-ASIC, DAQ-STC, Am9513

Figure 10-7 shows two ways to connect your counter to generate a square pulse. In the Basic Connection, the edges of the internal SOURCE signal are counted to generate the output signal, the GATE is not used (software start), and the pulse signal on the OUT pin gets connected to your device. For optional connections, you will acquire an external SOURCE from your device which is also gated by your device. You can use either or both of these options.

Chapter 10 High-Precision Timing (Counters/Timers)

Figure 10-7. Physical Connections for Generating a Square Pulse

Open the Generate Single Pulse (DAQ-STC), Generate Single Pulse (NI-TIO), or Generate Delayed Pulse-Easy (9513) examples and study their block diagrams.

The Generate Delayed Pulse VI, available on the Functions»Data Acquisition»Counter palette, tells your device to generate a single delayed pulse. This VI is self-contained and checks for errors automatically. With the Generate Delayed Pulse VI, you must connect the pulse delay (phase 1) and pulse width (phase 2) controls to define the output pulse. Sometimes the actual delay and actual width are not the same as you specified.

To gain more control over when the counter begins generating a single square pulse, use Intermediate VIs instead of the Easy VIs. You also can use the example Delayed Pulse-Int (9513) VI, available in the examples\ daq\counter\Am9513.llb. This example shows how to generate a single pulse using Intermediate level VIs. The Delayed Pulse Generator Config VI configures the counter, and the Counter Start VI generates the TTL signal. An example of this is generating a pulse after meeting certain conditions. If you use the Easy Counter VI, the VI configures and then immediately starts the pulse generation. With the Intermediate VIs, you can configure the counter long before the actual pulse generation begins. As soon as you want a pulse to be generated, the counter can immediately begin without having to configure the counter. In this situation, using

Chapter 10 High-Precision Timing (Counters/Timers)

Intermediate VIs improves performance. You must stop the counter if you want to use it for other purposes.

8253/54

Refer to the Delayed Pulse (8253) VI in the examples\daq\counter\ 8253.llb for an example of how to generate a negative polarity pulse. Due to the nature of the 8253/54 chip, three counters are used to generate this pulse. Because only counter 0 is internally connected to a clock source, it is used to generate the timebase. counter 1 is used to create the pulse delay that gates counter 2. counter 2 is used to generate the pulse, which occurs on the OUT pin. Using multiple counters requires external wiring, which is shown in Figure 10-8 and described on the front panel of the VI.

Figure 10-8. External Connections Diagram from the Front Panel of Delayed Pulse (8253) VI

The block diagram uses a sequence structure to divide the basic tasks involved. In frame 0 of the sequence all of the counters are reset. Notice that counters 1 and 2 are reset so their output states start out high.

In frame 1 of the sequence, the counters are set up for different counting modes. counter 0 is set up to generate a timebase using the ICTR Timebase Generator subVI. counter 1 is set up to toggle its output (low-to-high) when it reaches terminal count (TC). This toggled output is used to gate counter 2. counter 2 is set up to output a low pulse when its gate goes high.

In frame 2 of the sequence, a delay occurs so the delayed pulse has time to complete before the example can run again. This is useful if the example is used as a subVI that is called repeatedly.

While this example works well for most pulses, it has limitations when your pulse delay gets very short (in the microsecond range), or when the ratio of pulse delay to pulse width gets very large.