Chapter 10 High-Precision Timing (Counters/Timers)

Knowing the Accuracy of Your Counters

When you generate a waveform, there can be an uncertainty of up to one timebase period between the start signal and the first counted edge of the timebase. This is due to the uncertainty in the exact relation of the start signal, which the software calls or the gate signal supplies to the first edge of the timebase, as shown in Figure 10-13.

1 timebase period

timebase

starting signal

output

uncertainty of

1 timebase period

Figure 10-13. Uncertainty of One Timebase Period

8253/54

In addition to the previously described uncertainty, the 8253/54 chip has an additional uncertainty when used in mode 0. Mode 0 generates a low pulse for a chosen number of clock cycles, but a software delay is involved. This delay occurs because with mode 0 the counter output is set low by a software write to the mode setting. Afterward the count can be loaded and the counter starts counting down. The time between setting the output to low and loading the count is included in the output pulse. This time was found to be 20 s when tested on a 200 MHz Pentium computer.

Stopping Counter Generations

You can stop a counting operation in several ways. You can restart a counter for the same operation it just completed, you can reconfigure it to do something else, or you can call a specific VI to stop it. All of these methods allow you to use counters for different operations without resetting the entire device.

Chapter 10 High-Precision Timing (Counters/Timers)

DAQ-STC, Am9513

Figure 10-14 shows how to stop a counter using the Intermediate VI, Counter Stop. Notice that the Wait+ (ms) VI is called before Counter Stop. The Wait+ (ms) VI allows you to wire a time delay so that the previous counter operation has time to complete before the Counter Stop VI is called. The Wait+ (ms) and Counter Stop VIs are available on the

Functions»Data Acquisition»Counter»Intermediate Counter palette.

Figure 10-14. Using the Generate Delayed Pulse and Stopping the Counting Operation

To stop a generated pulse train, you can use another Generate Pulse

Train VI with the number of pulses input set to –1, shown in Figure 10-15. This example expects that a pulse train is already being generated. The call to Generate Pulse Train VI stops the counter, and the call to Generate Delayed Pulse VI sets the counter up for a different operation.

Figure 10-15. Stopping a Generated Pulse Train

8253/54

Calling ICTR Control VI with a control code of 7 (reset) can stop a counter on the 8253/54 chip.