Chapter 10 High-Precision Timing (Counters/Timers)

•An error has occurred.

•Your chosen time limit has been reached.

After the While Loop, the final count is subtracted from the originally loaded count of 65,535 and multiplied by the timebase period to yield the pulse width. Finally, the last ICTR Control VI resets the counter. Notice that this VI uses only Counter 0. If Counter 0 has an internal timebase of 2 MHz, the maximum pulse width you can measure is 216 × 0.5 µ s = 32 ms. Refer to the information found in Context Help for a complete description of this example.

Controlling Your Pulse Width Measurement

How you control your pulse-width measurement depends upon which counter chip is on your DAQ device. If you are not sure which counter chip your DAQ device has, refer to your hardware user manual.

TIO-ASIC, DAQ-STC, or Am9513

Figure 10-18 shows one approach to measuring pulse width using the Intermediate VIs Pulse Width or Period Meas Config, Counter Start, Counter Read, and Counter Stop. You can use these VIs to control when the measurement of the pulse widths begins and ends. The Pulse Width or Period Config VI configures a counter to count the number of cycles of a known internal timebase. The Counter Start VI begins the measurement. The Counter Read VI determines if the measurement is complete and displays the count value. After the While Loop is stopped, the Counter Stop VI stops the counter operation. Finally, the General Error Handler VI notifies you of any errors.

Figure 10-18. Measuring Pulse Width with Intermediate VIs