Chapter 10 High-Precision Timing (Counters/Timers)

7404

+5 V

TTL signal in

inverted TTL signal out

DGND

Figure 10-2. Wiring a 7404 Chip to Invert a TTL Signal

Note Refer to the VIs in the examples\daq\counter library for more information about the features of your counter chip.

Generating a Square Pulse or Pulse Trains

This section describes the ways you can generate a square pulse or multiple pulses (called pulse trains) using the counters available on your DAQ device with the example VIs in LabVIEW. All LabVIEW counter examples are in the examples\daq\counter library.

Generating a Square Pulse

There are many applications where you may need to generate TTL pulses. TTL pulses can be used as clock signals, gates, and triggers. You can use a pulse train of known frequency to determine an unknown TTL pulse width. You also can use a single pulse of known duration to determine an unknown TTL signal frequency, or use a single pulse to trigger an analog acquisition.

There are two basic types of counter signal generation—toggled and pulsed. When a counter reaches a certain value, a counter configured for toggled output changes the state of the output signal, while a counter configured for pulsed output outputs a single pulse. The width of the pulse is equal to one cycle of the counter SOURCE signal.

The following is a list of terms you should know before outputting a pulse or pulse train using LabVIEW:

•Phase 1 refers to the first phase or delay to the pulse.

•Phase 2 refers to the second phase or the pulse itself.

Chapter 10 High-Precision Timing (Counters/Timers)

•Period is the sum of phase 1 and phase 2.

•Frequency is the reciprocal of the period (1/period).

In LabVIEW, you can adjust and control the times of phase 1 and phase 2 in your counting operation. You do this by specifying a duty cycle. The duty cycle equals

phase 2,

--------------------

period

where period = phase 1 + phase 2.

Examples of various duty cycles are shown in Figure 10-3. The first line shows a duty cycle of 0.5, where phase 1 and phase 2 are the same duration. A signal with a 0.5 duty cycle acts as a SOURCE for counter operations. The second line shows a duty cycle of 0.1, where phase 1 has increased and phase 2 has decreased. The final line shows a large duty cycle of 0.9, where phase 1 is very short and the phase 2 duration is longer.

Figure 10-3. Pulse Duty Cycles

Note A high duty cycle denotes a long pulse phase relative to the delay phase.

How you generate a square pulse varies depending upon which counter chip your DAQ hardware has. If you are unsure which chip your device uses, refer to your hardware documentation.