Chapter 10 High-Precision Timing (Counters/Timers)

to count down. Inside the While Loop, ICTR Control reads the count, which is divided by the actual timebase frequency to determine the elapsed time. The elapsed time increments until you click the STOP button or an error occurs. The last two calls to ICTR Control reset Counter 0 and counter. Remember, you must externally wire the OUT of Counter 0 to the CLK of counter. You also can gate counter with a pulse to control when it starts and stops timing. To do this, wire your pulse to the GATE of counter. Refer to the information found in the Context Help for a complete description of this example.

Dividing Frequencies

Dividing TTL frequencies is useful if you want to use an internal timebase and the frequency you need does not exist. You can divide an existing internal frequency to get what you need. You also can divide the frequency of an external TTL signal. Frequency division results in a pulse or pulse train from a counter for every N cycles of an internal or external source. Counters can only decrease (divide down) the frequency of the source signal. The resulting frequency is equal to the input frequency divided

by N (timebase divisor). N must be an integer number greater than 1. Performing frequency division on an internal signal is called a down counter. Frequency division on an external signal is called a signal divider. Figure 10-29 shows typical wiring for frequency division.

Frequency Division for a Signal Divider

Frequency Division for a Down Counter

Figure 10-29. Wiring Your Counters for Frequency Division

Chapter 10 High-Precision Timing (Counters/Timers)

TIO-ASIC or DAQ-STC

Open the Generate Pulse Train (DAQ-STC) and Generate Pulse Train (NI-TIO) VIs, available in the examples\daq\counter library and study the block diagrams.

Am9513

Figure 10-30 shows an example of a signal divider. It uses the Intermediate counter VIs Down Counter or Divide Config, Counter Start, and

Counter Stop.

Figure 10-30. Programming a Single Divider for Frequency Division

The Down Counter or Divide Config VI configures the specified counter to divide the SOURCE signal by the timebase divisor value and output a signal when the counter reaches its terminal count (TC). Using Down Counter or Divide Config VI, you can configure the type of output to be pulsed or toggled. The block diagram in Figure 10-30 outputs a high pulse lasting one cycle of the source signal once the counter reaches its TC. The previous block diagram counts the rising edges of the SOURCE signal, the default value of the source edge input.

The Counter Start VI tells the counter to start counting the SOURCE signal edges. The counter stops the frequency division only when you click the STOP button. The Counter Stop VI stops the counter immediately and clears the count register. It is a good idea to always check your errors at the end of an operation to see if the operation was successful.

You can alter the Down Counter or Divide Config VI to create a down counter. To do this, change the timebase value from 0.0

(external SOURCE) to a frequency available on your counter. With the Am9513 chip, you can choose timebases of 1 MHz, 100 kHz, 10 kHz, 1 kHz, and 100 Hz. With the DAQ-STC chip, you can choose timebases of 20 MHz and 100 kHz.

Chapter 10 High-Precision Timing (Counters/Timers)

Instead of triggering frequency division for signal dividers and down counters by software, as previously described, you can trigger using the GATE signal. You can trigger while the GATE signal is high, low, or on the rising or falling edge.

8253/54

To divide a frequency with the 8253/54 counter chip, use the example Cont

Pulse Train (8253) VI, available in the examples\daq\8253.llb.

Part III

Measurement Analysis in LabVIEW

This part explains how to analyze your measurements in LabVIEW.

Part III, Measurement Analysis in LabVIEW, contains the following chapters:

•Chapter 11, Introduction to Measurement Analysis in LabVIEW, introduces digital signal processing and the LabVIEW Analysis VIs.

•Chapter 12, DC/RMS Measurements, describes how to use the two most common measurements of a signal.

•Chapter 13, Frequency Analysis, explains how to analyze dynamic signals using frequency analysis.

•Chapter 14, Distortion Measurements, explains harmonic distortion, THD, and SINAD.

•Chapter 15, Limit Testing, explains how to use limit testing, or mask testing, to monitor a waveform.

•Chapter 16, Digital Filtering, explains various types of filters you can use and how to decide which one to use.

•Chapter 17, Signal Generation, describes common test signals and how you can generate them.