values continuously in the array one point at a time at a specified rate. This is known as single-buffered waveform generation. But what if you want to generate a continually changing waveform? For example, you might have a large file stored on disk that contains data you want to output. Because LabVIEW cannot store the entire waveform in a single buffer, you must continually load new data into the buffer during the generation. This process requires the use of circular-buffered analog output in LabVIEW.

Letting an Outside Source Control Your Update Rate

DAQ devices use internal counters and timers to determine the rate of data generation. However, you might encounter times when you need to generate data in sync with other signals in your system. For example, you might need to output data to a test circuit every time that test circuit emits a pulse. In this case, internal counter/timers are inefficient for your needs. You need to control the update rate with your own external source of pulses.

Externally Controlling Your Update Clock

This section explains how to use these Intermediate VIs to generate data using an external update clock.

The update clock controls the rate at which digital-to-analog conversions occur. To control your data generation externally, you must supply this clock signal to the appropriate pin on the I/O connector of your DAQ device. The clock source you supply must be a TTL signal. Refer to the Generate N Updates-ExtUpdateClk VI in the examples\daq\ anlogout\anlogout.llb for an example of this process.

To use an external update clock, you must set the clock source of the

AO Start VI to I/O connector. When you connect your external clock, you find that different DAQ devices use different pins for this input. These input pins are described in Table 7-1.

Table 7-1. External Update Clock Input Pins

For waveform generation, you must supply an array of waveform data. The example Generate N Updates-ExtUpdateClk VI described previously uses data created in the Compute Waveform VI. When you run the example VI, the data is output on channel 0 (the DAC0OUT pin) of your DAQ device.

Supplying an External Test Clock from Your DAQ Device

To use an external update clock when you do not have an external clock available, create an external test clock using outputs from a counter/timer on your DAQ device, and then wire the output to your external update clock source.

If your DAQ device has an FOUT or FREQ_OUT pin, you can generate a 50% duty-cycle TTL pulse train using the Generate Pulse Train

on FOUT or FREQ_OUT VI, available in examples\daq\counter\ DAQ-STC.llb. The advantage of this VI is that it does not use one of the available counters, which you might need for other reasons.

You also can use the Pulse Train VIs to create an external test clock.

These VIs are located in examples\daq\counter\DAQ-STC.llb,

examples\daq\counter\NI-TIO.llb, examples\daq\counter\Am9513.llb, and examples\daq\counter\8253.llb.

Simultaneous Buffered Waveform

Acquisition and Generation

This section describes how to perform buffered waveform acquisition and generation simultaneously on the same DAQ device.

Using E Series MIO Boards

E series devices, such as the PCI-MIO-16E-1, have separate counters dedicated to analog input and analog output timing. For this reason, they are the best choice for simultaneous input/output.

Software Triggered

Open the Simul AI/AO Buffered (E Series MIO) VI, available in examples\daq\anlog_io\anlog_io.llb, and examine its block diagram.

This example VI uses Intermediate DAQ VIs. By following the error cluster wire, which enters each DAQ VI on the bottom left and exits on the bottom right, you can see that because of data dependency, the waveform generation starts before the waveform acquisition, and each task is configured to run continuously. This example VI is software-triggered, because it starts via software when you click the Run button.

Once you call the AO Start and AI Start VIs, the While Loop executes. Inside the While Loop, the AI Read VI returns acquired data from the analog input buffer. There is not a call to the AO Write VI inside the While Loop because it is not needed if the same data from the first AO Write VI is regenerated continuously. To generate new data each time the While Loop iterates, add an AO Write VI inside the While Loop. The While Loop stops when an error occurs or you click the Stop button. Your DAQ device resources are cleared by calling the AI Clear and AO Clear VIs after the loop stops.

Hardware Triggered

Open the Simul AI/AO Buffered Trigger (E Series MIO) VI, available in examples\daq\anlog_io\anlog_io.llb, and examine its block diagram.

Although this VI is similar to the Simul AI/AO Buffered (E Series MIO) VI described previously, it is more advanced because it uses a hardware trigger. The waveform acquisition trigger is set up with the trigger type input to the AI Start VI set to digital A (start), and by default this trigger is expected on the PFI0 pin. Hardware triggering for waveform generation requires an additional VI. The AO Trigger and Gate Config VI is an advanced analog output VI for E Series boards only. The trigger parameters are set using three inputs. The trigger or gate source is used to choose the source of your trigger, such as a PFI pin or a RTSI pin. The trigger or gate source specification is used in conjunction with the trigger or gate source to choose which PFI or RTSI pin number to use, such as 0 through 9 for a PFI pin. The trigger or gate condition is used to select a rising or falling trigger edge. The default analog output trigger for this example is a rising edge on PFI0. Because this is the same pin as the analog input trigger, the waveform acquisition and generation start simultaneously. However, they are not controlled by independent counter/timers, so you can run them at different rates.