TTL Signal

Figure 6-28. Example of a TTL Signal

Refer to the Acquire N Scans-ExtChanClk VI in the examples\daq\ anlogin\anlogin.llb for an example of how to set up your acquisition for an externally controlled channel clock. The VI includes the AI Clock Config VI and the clock source connected to the I/O connector.

You can enable external conversions by calling the advanced-level

AI Clock Config VI. Remember that the AI Clock Config VI, which is called by the AI Config VI, normally sets internal channel delay automatically or manually with the interchannel delay control. However, calling the AI Clock Config VI after the AI Config VI resets the channel clock so that it comes from an external source for external conversion. Also, notice that the scan clock is set to 0 to disable it, allowing the channel clock to control the acquisition rate.

Note The 5102 devices do not support external channel clock pulses, because there is no channel clock on the device.

On most devices, external conversions occur on the falling edge of the EXTCONV* line. Consult your hardware reference manual for timing diagrams. On devices with PFI lines (such as E Series devices), you can set the Clock Source Code input of AI Clock Config VI to the PFI pin with either falling or rising edge or use the default PFI2/Convert* pin where the conversions occur on the falling edge.

Because LabVIEW determines the length of time before the AI Read VI times out based on the interchannel delay and scan clock rate, you may need to force a time limit for the AI Read VI, as illustrated in the Acquire N Scans-ExtChanClk VI described previously.

Note On the Lab-PC+ and 1200 devices, the first clock pulse on the EXTCONV* pin configures the acquisition but does not cause a conversion. However, all subsequent pulses cause conversions.