Chapter 10 High-Precision Timing (Counters/Timers)

Generating a Pulse Train

There are two types of pulse trains: continuous and finite. You can use a continuous pulse train as the SOURCE (CLK) of another counter or as the clock for analog acquisition (or generation). You can use a finite pulse train as the clock of an analog acquisition that acquires a predetermined number of points, or to provide a finite clock to an external circuit.

Generating a Continuous Pulse Train

How you generate a continuous pulse varies depending upon which counter chip your DAQ hardware has. If you are not sure which chip your device uses, refer to your hardware manual.

TIO-ASIC, DAQ-STC, Am9513

Figure 10-9 shows how to connect your counter and device to generate a continuous pulse train. The edges of the internal source signal are counted to generate the output signal. You obtain the continuous pulse train for your external device from the counter OUT pin. You also can gate the operation with a signal connected to the GATE input pin. Instead of having an internal timebase as your SOURCE, you can connect an external signal.

Figure 10-9. Physical Connections for Generating a Continuous Pulse Train

Open the Generate Pulse Train (DAQ-STC), Generate Pulse Train (NI-TIO), or Cont Pulse Train-Easy (9513) VIs, available in the examples\daq\counter library and study their block diagrams.

Chapter 10 High-Precision Timing (Counters/Timers)

8253/54

Figure 10-10 shows how to connect your counter and device to generate a continuous pulse train. If you use counter 0, an internal source is counted to generate the output signal. If you use counter 1 or 2, you will need to connect your own source to the CLK pin. You obtain the continuous pulse train for your external device from the counter OUT pin.

Figure 10-10. External Connections Diagram from the Front Panel of Cont Pulse Train (8253) VI

Refer to the Cont Pulse Train (8253) VI in the examples\daq\counter\ 8253.llb for an example of how to use the Generate Pulse Train (8253) VI to generate a continuous pulse train. When using counter 0 with this VI, you can specify the desired frequency. The actual frequency shows the closest frequency to your desired frequency that the counter was able to achieve. The actual duty cycle will be as close to 0.5 as possible for your actual frequency. When using counter 1 or counter 2, you specify the divisor factor N to be used to divide your supplied source. You also can enter the user-supplied timebase if you want the VI to calculate your actual frequency and actual duty cycle. When you click the STOP button, the While Loop stops, and a call to ICTR Control resets the counter, stopping the generation.

Generating a Finite Pulse Train

How you generate a finite pulse varies depending upon which counter chip your DAQ hardware has. If you are not sure which chip your device uses, refer to your hardware manual.

You can use the Easy I/O VI, Generate Pulse Train, or a stream of Intermediate VIs to generate a finite pulse train. With either technique, you must use two counters as shown in Figure 10-11. The maximum number of pulses in the pulse train is 216–1 for Am9513 devices and 224–1 for DAQ-STC devices.

Chapter 10 High-Precision Timing (Counters/Timers)

Figure 10-11 shows the physical connections to produce a finite pulse train on the OUT pin of a counter. counter generates the finite pulse train with high-level gating. counter-1 provides counter with a long enough gate pulse to output the number of desired pulses. You must externally connect the OUT pin of the counter-1 to the GATE pin of counter. You also can gate counter-1.

Figure 10-11. Physical Connections for Generating a Finite Pulse Train

Open the Finite Pulse Train (DAQ-STC), Finite Pulse Train (NI-TIO), or Finite Pulse Train-Easy (9513) VIs, available in the examples\daq\ counter library, and study the block diagrams.

8253/54

Generating a finite pulse train with the 8253/54 chip uses all three counters. Figure 10-12 shows how to externally connect your counters. Because counter 0 is internally connected to a clock source, counter 0 is used to generate the timebase used by counter 1 and counter 2. counter 1 generates a single low pulse used to gate counter 2. Because counter 2 must be gated with a high pulse, the output of counter 1 is passed through a 7404 inverter chip prior to being connected to the GATE of counter 2. counter 2 is set up to generate a pulse train at its OUT pin.

Figure 10-12. External Connections Diagram from the Front Panel of Finite Pulse Train (8253) VI

Refer to the Finite Pulse Train (8253) VI in the examples\daq\ counter\8253.llb for an example of how to generate a finite pulse train. This example uses a sequence structure to divide the basic tasks involved. In frame 0 of the sequence, all of the counters are reset. Notice counter 1 is reset so its output state starts high.