496In bidirectional systems, there is a remote chance of erroneous behavior due to EMI that could result in bus

497contention. Mechanisms are provided in this specification for recovering from any bus contention event

498without forcing “hard reset” of the entire system.

4995.6 Clock Management

500DSI Clock is a signal from the host processor to the peripheral. In some systems, it may serve multiple

501functions:

502DSI Bit Clock: Across the Link, DSI Clock is used as the source-synchronous bit clock for capturing serial

503data bits in the receiver PHY. This clock shall be active while data is being transferred.

504Byte Clock: Divided down, DSI Clock is used to generate a byte clock at the conceptual interface between

505the Protocol and Application layers. During HS transmission, each byte of data is accompanied by a byte

506clock. Like the DSI Bit Clock, the byte clock shall be active while data is being transferred. At the Protocol

507layer to Application layer interface, all actions are synchronized to the byte clock.

508Application Clock(s): Divided-down versions of DSI Bit Clock may be used for other clocked functions at

509the peripheral. These “application clocks” may need to run at times when no serial data is being transferred,

510or they may need to run constantly (continuous clock) to support active circuitry at the peripheral. Details

511of how such additional clocks are generated and used are beyond the scope of this specification.

512For continuous clock behavior, the Clock Lane remains in high-speed mode generating active clock signals

513between HS data packet transmissions. For non-continuous clock behavior, the Clock Lane enters the LP-

51411 state between HS data packet transmissions.

5155.6.1 Clock Requirements

516All DSI transmitters and receivers shall support continuous clock behavior on the Clock Lane, and

517optionally may support non-continuous clock behavior. A DSI host processor shall support continuous

518clock for systems that require it, as well as having the capability of shutting down the serial clock to reduce

519power.

520Note that the host processor controls the desired mode of clock operation. Host protocol and applications

521control Clock Lane operating mode (High Speed or Low Power mode). System designers are responsible

522for understanding the clock requirements for peripherals attached to DSI and controlling clock behavior in

523accordance with those requirements.

524Note that in Low Power signaling mode, LP clock is functionally embedded in the data signals. When LP

525data transmission ends, the clock effectively stops and subsequent LP clocks are not available to the

526peripheral. If the peripheral requires additional clocks to advance the state of its logic, to move date through

527sequential buffers, or similar, it may be necessary to add ‘dummy’ data bytes to the LP transmission to

528effect forward progress of state machines or to advance data through sequential logic.

529The handshake process for BTA allows only limited mismatch of Escape Mode clock frequencies between

530a host processor and a peripheral. The Escape Mode frequency ratio between host processor and peripheral

531shall not exceed 3:2. The host processor is responsible for controlling its own clock frequency to match the

532peripheral. The host processor LP clock frequency shall be in the range of 67% to 150% of peripheral LP

533clock frequency. Therefore, the peripheral implementer shall specify a peripheral’s nominal LP clock

534frequency and the guaranteed accuracy.

Copyright © 2005-2006 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member Confidential.

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5355.6.2 Clock Power and Timing

536Additional timing requirements in MIPI Alliance Standard for D-PHY [4] specify the timing relationship

537between the power state of data signal(s) and the power state of the clock signal. It is the responsibility of

538the host processor to observe this timing relationship. If the DSI Clock runs continuously, these timing

539requirements do not apply.

Copyright © 2005-2006 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member Confidential.

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