Version 1.00a 19-Apr-2006 |
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MIPI Alliance Standard for DSI |
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1347
1348
1349 Figure 22 DSI Video Mode Interface Timing: Burst Communication
1350 8.11.5 Parameters
1351 Table 19 documents the parameters used in the preceding figures. Peripheral supplier companies are 1352 responsible for specifying suitable values for all blank fields in the table. The host processor shall meet 1353 these requirements to ensure interoperability.
1354 For periods when Data Lanes are in LP Mode, the peripheral shall also specify whether the DSI Clock Lane 1355 may go to LP. The host processor is responsible for meeting minimum timing relationships between clock 1356 activity and HS transmission on the Data Lanes as documented in MIPI Alliance Standard for D-PHY [4].
1357 |
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Table 19 Required Peripheral Timing Parameters |
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Parameter |
Description |
Minimum |
Maximum |
Units |
Comment |
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brPHY |
Bit rate total on all Lanes |
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Mbps |
Depends on PHY |
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implementation |
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tL |
Line time |
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μs |
Define range to meet |
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frame rate |
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tHBP |
Horizontal back porch |
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μs |
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tHACT |
Time for image data |
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μs |
Defining min = 0 allows |
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max PHY speed |
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HACT |
Active pixels per line |
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pixels |
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tHFP |
Horizontal front porch |
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μs |
No upper limit as long as |
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line time is met |
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Copyright © 2005-2006 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member Confidential.
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