Index

0-address format architecture, 17

1-address format architecture, 17

2-address format architecture, 18

3-address format architecture, 18 80/20 rule, 15

absolute addressing mode, 20 accumulator, 12 accumulator architecture, 17 actual accuracy, 48

ADC, 42

actual accuracy, 48 bipolar, 50 conversion time, 43 differential input, 50

differential non-linearity, 48 flash converter, 45

gain amplification, 50 gain error, 48

integral non-linearity, 48 offset error, 48 quantization error, 48 sample/hold, 44 single-ended conversion, 50

successive approximation converter, 46 tracking converter, 46

transfer function, 43 unipolar, 50

addressing modes absolute, 20 autodecrement, 20 autoincrement, 20 based, 20

direct, 20 displacement, 20 immediate, 20 indexed, 20 literal, 20

memory indirect, 20 register, 20

register indirect, 20

alternate functions of port pins, 33 ALU, 12

analog comparator, 41 analog I/O

analog-to-digital converter (ADC), 42 comparator, 41

conversion trigger, 49 digital-to-analog converter (DAC), 40 granularity, 43

meta-stability, 42 R-2R resistor ladder, 41 reference voltage, 44 resolution, 43

word width, 43

analog-to-digital converter (ADC), 42 arithmetic logic unit, 12 asynchronous interface, 73

atomic action, 52 atto, 8

autodecrement addressing mode, 20 autoincrement addressing mode, 20 avalanche injection, 28

based addressing mode, 20 baud rate, 75

baud rate register, 77 bi-directional communication, 74 Big Endian, 31

binary-weighted resistor, 41 bipolar, 50

bit-banging, 84

bits per second (bps), 75 BOR, 71

brown-out reset, 71 bus, 73

capacitor, 26 charge pumps, 29

Complex Instruction Set Computer, 15

94

computer operates properly, 68 condition code register, 12 continuous mode, 49

control unit, 11, 14 controller family, 3 conversion time, 43 COP, 68

counter, 60

DAC, 40

R-2R resistor ladder, 41 RC low-pass filter, 40

data direction register, 33 data memory, 22

data path, 11 differential inputs, 50 differential interface, 74

differential non-linearity, 48 digital I/O, 33

synchronizer, 35 alternate functions, 33 data direction register, 33 floating pin, 37

input delay, 35 meta-stability, 35 noise cancellation, 37 open drain input, 37 port, 33

port input register, 33 port register, 33

pull resistor, 37 sink input, 38 sink output, 38 source input, 38 source output, 38

Digital Signal Processor, 7 digital-to-analog converter (DAC), 40 direct addressing mode, 20 displacement addressing mode, 20 DNL, 48

DRAM, 26 DSP, 7

Dynamic Random Access Memory, 26

EEPROM, 29

Embedded Processor, 7

Embedded System, 7

EPROM, 28

INDEX

event

interrupt, 52 polling, 52

exa, 8

excess representation, 50 external event, 55 external reset, 71

femto, 8 FETs, 28

field effect transistors, 28 Flash, 29

flash converter, 45 floating gate, 28 floating pin, 37 full-duplex, 74

gain amplification, 50 gain error, 48

general-purpose registers, 20 giga, 8

glitch, 65

global interrupt enable, 52 granularity (ADC), 43 granularity (timer), 61

half-duplex, 74 hard-wired, 14

Harvard Architecture, 15

IIC, 83 dominant, 84 recessive, 84

immediate addressing mode, 20 index register, 12

indexed addressing mode, 20 INL, 48

input capture, 62 accuracy, 63

input delay, 35 instruction memory, 22 instruction register, 14 instruction set, 15

arithmetic-logic instructions, 18 control instructions, 19

data transfer instructions, 19 execution speed, 18 instruction size, 16 orthogonal, 20

INDEX

program flow instructions, 19 integral non-linearity, 48 Inter-IC, 83

interface asynchronous, 73 bus, 73 differential, 74 full-duplex, 74 half-duplex, 74 master-slave, 74

multi-drop network, 73 parallel, 73 point-to-point, 73 RS-232, 80

RS-422, 80

RS-485, 80 serial, 73

Serial Communication Interface, 75 single-ended, 74

SPI, 82 synchronous, 73 UART, 75 USART, 81

internal events, 55 internal reset, 71 interrupt

enable bit, 52 flag bit, 52 ISR, 52 latency, 56 mode, 52 NMI, 53

non-maskable, 53 service routine, 52 spurious, 55 vector, 53

vector table, 53

interrupt service routine, 52, 57 interrupts, 52

ISR, 52

jitter, 59

kilo, 8

leakage currents, 26 level interrupt, 52

literal addressing mode, 20

95

Little Endian, 31

load/store architecture, 18, 20

Mask-ROM, 27 master-slave, 74 mega, 8 Memory, 22

data memory, 22 DRAM, 26

dynamic random access memory, 26 EEPROM, 28

electrically erasable programmable read-only memory, 28

EPROM, 28

erasable programmable read-only memory, 28 Flash EEPROM, 29

instruction memory, 22 non-volatile, 27 non-volatile RAM, 29 NVRAM, 29

programmable read-only memory, 27 PROM, 27

read-only memory, 27 register file, 22 ROM, 27

SRAM, 23

static random access memory, 23 volatile, 23

memory indirect addressing mode, 20 meta-stability, 35, 42

micro, 8 Microcontroller, 7 microinstructions, 14 Microprocessor, 6 milli, 8

MISO, 82

Mixed-Signal Controller, 7 modulus mode, 60

MOSI, 82

most significant bit, 12 MROM, 27

multi-drop networks, 73

nano, 8 negative-logic, 33 nested interrupt, 54 NMI, 53

noise cancellation, 37, 55, 65

96

Non Return to Zero, 76 non-maskable interrupt, 53 non-volatile memory, 27 Non-Volatile RAM, 29 NRZ, 76

NVRAM, 29 Nyquist criterion, 44

offset error, 48

One Time Programmable EPROMs, 28

One Time Programmable microcontrollers, 28 one’s complement, 12

open-drain input, 37 orthogonal instruction set, 20 OTP, 28

OTP-EPROMs, 28 output compare, 65

parallel interface, 73 parity bit, 75

peta, 8 pico, 8

point-to-point, 73 polling, 52

POR, 71

port input register, 33 port register, 33 ports, 33 positive-logic, 33

power consumption, 69 power prefixes, 8 power save

clocking frequency reduction, 69 module shutdown, 69

optimized design, 70 voltage reduction, 69

power-on reset, 71 prescaler, 61, 63 processor, 7 program counter, 14

Programmable Read Only Memory, 28 PROM, 28

pull resistor, 37

pulse width modulation, see PWM glitch, 65

up-counter, 65 up-down-counter, 66

PWM, 40, 65

INDEX

quantization error, 48

R-2R resistor ladder, 41 RAM, 23

RC low-pass filter, 40 read-modify-write, 34, 53 read-only memory, 27 real-time clock, 62 Real-Time System, 7

Reduced Instruction Set Computer, 15 reference voltage, 44

register addressing mode, 20 register file, 22

register indirect addressing mode, 20 reset, 70

brown-out reset, 71 external reset, 71 internal reset, 71 power-on reset, 71 watchdog reset, 71

reset routine, 70 resolution (ADC), 43 resultion (timer), 60 ROM, 27

RS-232, 80

RS-422, 80

sample/hold stage, 44 SAR, 47

SCI, 75

SCK, 82

SCL, 83

SDA, 83

Serial Clock Line, 83

Serial Communication Interface, 75 Serial Data Line, 83

serial interface, 73

Serial Peripheral Interface, 82 Shannon’s sampling theorem, 44 single conversion mode, 49 single-ended conversion, 50 single-ended interface, 74

sink input, 38 sink output, 38 sleep modes, 69 source input, 38 source output, 38 SPI, 82

INDEX

MISO, 82

MOSI, 82

SCK, 82

SS, 82

spurious interrupts, 55 SRAM, 23

SS, 82 stack, 13

stack architecture, 17 stack pointer, 13

Static Random Access Memory (SRAM), 23 status register, 12

successive approximation converter, 46 successive approximation register, 47 synchronizer, 35

synchronous interface, 73

tera, 8 timer, 60

asynchronous mode, 62 external, 62 granularity, 61

input capture, 62 internal clock, 60 modulus mode, 60 output compare, 65 prescaled, 61

pulse accumulator, 62 pulse width modulation, 65 resolution, 60

system clock, 60 timestamping accuracy, 63 tracking converter, 46 transfer function, 43 transistor

FET, 28

field effect transistor, 28 TWI, 84

two’s complement, 12, 50 Two-wire Interface, 84

UART, 75

baud rate, 75

baud rate register, 77 data overrun, 77 frame error, 77 oversampling, 76 parity, 75

97

parity error, 77 unipolar, 50

Universal Asynchronous Receiver Transmitter, 75 Universal Synchronous Asynchronous Receiver Trans-

mitter, 81 USART, 81

variable size instructions, 17 volatile memory, 23

Von Neumann Architecture, 15 von Neumann bottleneck, 15

watchdog reset, 71 watchdog timer, 68 Wilkes, Maurice, 14 wired-AND, 84 wired-NOR, 84 word width, 43

yocto, 8 yotta, 8

zepto, 8 zetta, 8