Index

A

ARESETn

AWBURST

2-3

description 2-2

encoding

4-5

ACLK

timing 11-2

AWCACHE

2-3

description 2-2

ARID 2-6

encoding

5-3

Address channel 1-3

in exclusive accesses 6-4, 6-5

in exclusive accesses

6-5

definition

1-4

out-of-order transactions 8-2

AWID 2-3

handshake 1-4, 3-2

uniqueness 8-9

in exclusive accesses

6-5

Address ID tag

ARLEN 2-6

out-of-order transactions 8-2

see ARID and AWID

encoding

4-3

uniqueness 8-9

Addressing options

4-2

ARLOCK 2-6

AWLEN 2-3

Allocate attribute 1-11

encoding

6-2

encoding

4-3

AMBA

ARPROT 2-6

AWLOCK

2-3

architecture xiv

encoding

5-6

encoding

6-2

interface

1-2

ARREADY

2-6

AWPROT 2-3

Specification xvii

timing example

1-7, 1-8

encoding

5-6

ARADDR 2-6

ARSIZE 2-6

AWREADY

2-3

timing example

1-7, 1-8

encoding

4-4

timing example

1-9

ARBURST

2-6

ARVALID

2-6

AWSIZE 2-3

encoding

4-5

reset 11-2

encoding

4-4

ARCACHE

2-6

timing example

1-7, 1-8

AWVALID

2-3

encoding

5-3

Atomic access encoding 6-2

reset 11-2

in exclusive accesses 6-5

AWADDR

2-3

timing example

1-9

timing example

1-9

ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

Index-1

AXI protocol

CACTIVE 2-8

12-4, 12-5

G

features

1-2

timing example

Channel register insertion 1-6

Global signals 2-2

B

Clock 11-2

Completion signaling 1-5, 7-2, 7-4, 7-5

H

BID 2-5

see also BRESP

see also RRESP

out-of-order transactions

8-2

Conventions

Handshake

Big-endian data structures

9-5

signal naming

xvii

address channel 3-2

BREADY

2-5

timing diagram

xvi

read address channel 3-4

default value

3-4

typographical

xv

read data channel

3-2, 3-5

timing example

1-9

CSYSACK

2-8

signal dependencies

3-7

BRESP 2-5

timing example

12-4, 12-5

timing example

3-3

encoding

7-2

CSYSREQ 2-8

write address channel

3-3

in exclusive accesses 6-6

timing example

12-4, 12-5

write data channel 3-2, 3-4

timing example

1-9

write response channel 3-2, 3-4

Bufferable attribute

1-11

D

selecting

5-2

I

Burst

4-7

Data bus

address

length

4-7

narrow transfers

9-4

Incrementing bursts

Burst length

4-3

width 1-5

byte lanes

4-4, 4-8

encoding

4-3

DECERR response

7-2, 7-5

increment value

4-5

Burst size

4-4

Decode error

narrow 4-4

encoding

4-4

see DECERR response

start address 4-7

Burst type

4-5

Direct memory access

Interconnect

encoding

4-5

see DMA

combining data streams

8-6

fixed 4-5

DMA, support 1-2

implementations

1-6

incrementing

4-5

locked accesses

6-7

wrapping 4-6

E

out-of-order transactions

1-9, 8-6

BVALID

2-5

realigning address and data 3-6

reset requirements 11-2

Interleaved transactions

timing example

1-9

Exclusive access

see Out-of-order transactions

Byte lane strobes

1-5

selecting

6-2

see also WSTRB

slave support logic 6-3

L

Byte lanes

Exclusive access response

eight-bit transfer example 9-4

see EXOKAY response

32-bit transfer example

9-4

EXOKAY response

6-3, 6-5, 7-2, 7-4

Little-endian data structures

9-5

Byte-invariant endianness

9-5

Locked access

F

interconnect 6-7

C

selecting

6-2

Fixed bursts

4-5

Low-power interface

signals 2-8

Cache

byte lanes

4-4, 4-8

support

5-2

start address

4-7

M

Cache encoding

5-3

Cacheable attribute

1-11

selecting

5-2

Master slave handshake

1-4, 1-7, 3-2

timing example

3-2, 3-3

Index-2

Copyright © 2003, 2004 ARM Limited. All rights reserved.

ARM IHI 0022B

N

RREADY 2-7

3-5

U

default value

Normal access success

timing example

1-7, 1-8

Unaligned transfers

10-1

see OKAY response

RRESP

2-7

examples

10-3, 10-4

encoding 7-2

signaling unaligned start address

O

in exclusive accesses

6-6

10-2

RVALID

2-7

11-2

reset requirements

V

OKAY response

6-4, 6-5, 7-2, 7-4

timing example

1-7, 1-8

Out-of-order transactions 1-3, 1-9

from one master

8-3

S

Virtual masters 1-10

interconnect

1-9, 8-2

write reorder depth 8-6

W

Signal naming conventions

xvii

P

Signals

global

2-2

2-8

WDATA

2-4

1-9

low-power interface

timing example

Parallel transaction processing 1-6,

read address channel

2-6

WID 2-4

1-8, 8-2

read data channel

2-7

out-of-order transactions

8-2

Peripheral clock control 12-3

write address channel

2-3

uniqueness

8-9

Protection

write data channel

2-4

WLAST 2-4

encoding

5-6

write response channel

2-5

timing example

1-9

Protection level

Slave error response

Wrapping bursts

selecting

5-5

see SLVERR response

byte lanes

4-4, 4-8

SLVERR response

7-2, 7-4

length

4-3, 4-6

R

narrow

4-4

T

start address 4-6, 4-7

RDATA 2-7

wrap boundary

4-6, 4-7

WREADY

2-4

timing example

1-7, 1-8

Timing diagram conventions xvi

timing example

1-9

Read address channel

Transaction attributes

1-11

Write address channel

handshake

3-4

Transaction ID tag

1-9, 1-10

handshake

3-3

signals 2-6

interconnect

8-9

signals

2-3

Read allocate attribute

see also ARID and AWID

Write allocate attribute

selecting

5-2

see also RID

selecting 5-2

Read data channel

1-3

see also WID

Write data channel

1-3

definition

1-5

Transaction order

byte lane strobes

1-5

handshake

1-4, 3-2, 3-5

read transactions

8-4

definition

1-5

signals 2-7

rules

8-3

handshake

1-4, 3-2, 3-4

Read ID tag

see also Out-of-order transactions

signals

2-4

see RID

write data interleaving

8-6

Write data interleaving depth

8-6

Register insertion

1-6

write reorder depth

8-6

Write ID tag

Reset 11-2

write transactions

8-5

see WID

Response signaling

7-2

Typographical conventions

xv

Write response channel 1-3

RID 2-7

definition

1-5

out-of-order transactions 8-2

handshake

1-4, 3-2, 3-4

uniqueness 8-9

signals

2-5

RLAST 2-7

Write strobe signals

timing example

1-7, 1-8

see WSTRB

ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

Index-3

Index-4

Copyright © 2003, 2004 ARM Limited. All rights reserved.

ARM IHI 0022B