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Introduction

1.2Architecture

The AXI protocol is burst-based. Every transaction has address and control information on the address channel that describes the nature of the data to be transferred. The data is transferred between master and slave using a write data channel to the slave or a read data channel to the master. In write transactions, in which all the data flows from the master to the slave, the AXI protocol has an additional write response channel to allow the slave to signal to the master the completion of the write transaction.

The AXI protocol enables:

address information to be issued ahead of the actual data transfer

support for multiple outstanding transactions

support for out-of-order completion of transactions.

Figure 1-1 shows how a read transaction uses the read address and read data channels.

 

 

 

 

 

 

 

Read address channel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slave

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interface

 

 

 

 

 

Read data channel

 

 

 

interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

 

Read

 

Read

 

Read

 

 

 

 

 

 

 

data

 

 

data

 

data

 

data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1-1 Channel architecture of reads

Figure 1-2 on page 1-4 shows how a write transaction uses the write address, write data, and write response channels.

ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

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