Ordering Model

8.7Interconnect use of ID fields

When a master interface is connected to an interconnect, the interconnect appends additional bits to the ARID, AWID and WID fields that are unique to that master port. This has two effects:

•masters do not have to know what ID values are used by other masters, because the interconnect makes the ID values unique when it appends the master number to the field

•the width of the ID field at a slave interface is wider than the ID field at a master interface.

For read data, the interconnect uses the additional bits of the RID field to determine which master port the read data is destined for. The interconnect removes these bits of the RID field before passing the RID value to the correct master port.

Ordering Model

8.8Recommended width of ID fields

To take advantage of the AXI out-of-order transaction capability, use the following recommendations:

•implement a transaction ID up to four bits in master components

•implement up to four additional bits of transaction ID for master port numbers in the interconnect

•implement eight bits of ID support in slave components.

Note

For masters that support only a single ordered interface, it is acceptable to tie the ID outputs to a constant value, such as 0.

For slaves which do not make use of the ordering information and simply process all transactions in order, it is possible to use a standard off-the-shelf module to add the ID functionality to the slave, therefore making it possible to design the base functionality of the slave without the ID signaling present.