Low-power Interface
12.2.4Clock control sequence summary
Figure 12-4 shows the typical flow for entering and exiting a low-power state.
Normal |
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clocked |
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operation |
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System clock controller |
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Low -pow er |
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drives CSYSREQ low to |
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request low -pow er |
entry |
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Peripheral |
denies |
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Peripheral |
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system |
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clock controller |
initiates |
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accepts |
request |
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low -pow er |
exit |
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System clock |
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Deny |
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A ccept |
Peripheral |
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controller |
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Peripheral keeps |
Peripheral perf orms |
Peripheral |
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System clock controller |
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enables |
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CACTIV E HIGH |
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pow er-dow n |
CACTIV E HIGH |
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clocks |
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Peripheral drives |
Peripheral drives |
System clock controller |
System clock controller |
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CSYSACK LOW to |
immediately |
enables |
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CACTIV E LOW |
drives CSYSREQ HIGH |
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acknow ledge request |
clocks |
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System clock controller |
Peripheral drives |
System clock controller |
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Peripheral |
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CSYSACK LOW to |
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samples CACTIV E |
drives CSYSREQ HIGH |
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CACTIV E |
HIGH |
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acknow ledge request |
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System clock controller |
System clock controller |
Peripheral |
drives |
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Peripheral |
drives |
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CSYSACK HIGH to |
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CSYSACK HIGH to |
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drives CSYSREQ HIGH |
samples CACTIV E |
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complete handshake |
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complete handshake |
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Peripheral drives |
System clock controller |
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CSYSACK HIGH to |
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disables clocks |
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complete handshake |
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Figure 12-4 Low-power clock control sequence
12-6 |
Copyright © 2003, 2004 ARM Limited. All rights reserved. |
ARM IHI 0022B |
Low-power Interface
12.2.5Combining peripherals in a low-power domain
The system clock controller can combine a number of different peripherals within the same low-power clock domain. Then the clock domain can be treated in the same way as a single peripheral if the following rules are observed:
•The clock domain CACTIVE signal is the logical OR of all the CACTIVE signals within the clock domain. This means that the system clock controller can disable the clocks only when all peripherals indicate that they can be disabled.
•The system clock controller can use a single CSYSREQ signal that is routed to all peripherals within the clock domain.
•The clock domain CSYSACK signal is generated as follows:
—the falling edge of CSYSACK occurs when the last falling edge from all of the peripherals occurs
—the rising edge of CSYSACK occurs when the last rising edge from all of the peripherals occurs.
ARM IHI 0022B |
Copyright © 2003, 2004 ARM Limited. All rights reserved. |
12-7 |
Low-power Interface
12-8 |
Copyright © 2003, 2004 ARM Limited. All rights reserved. |
ARM IHI 0022B |