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Chapter 7

Response Signaling

This chapter describes the four slave responses in AXI read and write transactions. It contains the following sections:

About response signaling on page 7-2

Response types on page 7-4.

ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

7-1

Response Signaling

7.1About response signaling

The AXI protocol allows response signalling for both read and write transactions. For read transactions the response information from the slave is passed alongside the read data itself, however for writes the response information is conveyed along the write response channel.

The AXI protocol responses are:

OKAY

EXOKAY

SLVERR

DECERR.

Table 7-1 shows the encoding of the RRESP[1:0] and BRESP[1:0] signals.

 

 

Table 7-1 RRESP[1:0] and BRESP[1:0] encoding

 

 

 

RRESP[1:0]

 

 

BRESP[1:0]

Response

Meaning

 

 

 

b00

OKAY

Normal access okay indicates if a normal access has been successful. Can also indicate

 

 

an exclusive access failure.

 

 

 

b01

EXOKAY

Exclusive access okay indicates that either the read or write portion of an exclusive access

 

 

has been successful.

 

 

 

b10

SLVERR

Slave error is used when the access has reached the slave successfully, but the slave

 

 

wishes to return an error condition to the originating master.

 

 

 

b11

DECERR

Decode error is generated typically by an interconnect component to indicate that there

 

 

is no slave at the transaction address.

 

 

 

For a write transaction, there is just one response given for the entire burst and not for each data transfer within the burst.

In a read transaction, the slave can give different responses for different transfers within a burst. In a burst of 16 read transfers, for example, the slave might return an OKAY response for 15 of the transfers and a SLVERR response for one of the transfers.

The protocol defines that the required number of data transfers must be performed, even if an error is reported. For example, if a read of 8 transfers is requested from a slave but the slave has an error condition then the slave must perform 8 data transfers, each with an error response. The remainder of the burst is not cancelled if the slave gives a single error response.

7-2

Copyright © 2003, 2004 ARM Limited. All rights reserved.

ARM IHI 0022B

Response Signaling

This protocol places restrictions on masters that can issue multiple outstanding addresses and that must also support precise error signaling. Such masters must be able to handle an error response for an earlier transfer while later transfers are already underway.

ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

7-3

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