Embedded Systems Design - An Introduction to Processes Tools and Techniques (A. Berger, 2002)
.pdfemulator xxv, 41, 111, 120–125, 165
See also emulator,ROM shadow 166
space xxiv RTE 75
RTOS xx, 23, 32–37, 64–65, 80, 102, 116, 133, 197, 202 and performance 202
and watchdog 104 |
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availability 32 |
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checklist 33 |
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debugging tools 36 |
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device drivers 35 |
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integration testing 195 |
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performance 35 |
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services 37 |
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support 39 |
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technical support 36 |
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RTS 75, 77 |
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run control 15, 116, 166, 173, 179 |
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run-time environment 70, 77–81 |
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run-time library 80 |
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safety critical 81 |
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safety factor 73 |
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sampling 144 |
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sanity check 103 |
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selection process 21, 41 |
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self-test 78, 103 |
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semiconductor |
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manufacturer |
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See chip vendor |
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shadow |
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memory 175 RAM 166 register 93 ROM 166
shared library 84 shift register 155 shrink 25 side-effect 93 signal intrusion 125 signature words 73 silicon compilation
See VHDL simulation 60
bus functional model 62 hardware 60
simulator architectural 115 instruction
See ISS
VHDL 196 single-step 116, 119 skew 173, 180
Team-Fly®
sleep mode xxi SoC 55, 60, 209 socket adapter 172 software architecture 14 interrupt xxiv, 116 mission-critical 186 safety-critical 186 SOS
See SoC
source module 83 SP 73–74 specifications product 4–7 timing 178 SPECmark 31
speed vs density 95 S-Record 87
stack 70–71, 73, 75, 90 depth checking 103 frame 71, 77, 91 location 71
overflow 73 pointer 73 protocol 90 startup
code 39, 78–80 vector 78 state
modes 131 transition 133, 136
statechart 106, 108–109 statement coverage 192, 198
See also testing static storage 71
statistical profiling 142 status bits 94
stress tests 191 structured analysis 107 stub code 49, 61
substitution memory xxv, 15, 180
See also overlay memory symbol
external 86 internal 86
symbol table 69, 83, 86, 132 symbolic trigger 133 synchronization 99
system
integrity check 78 recovery 105
startup xxiv, 70, 73–80 system integration 194 system space 71 system-on-silicon
See SoC
T
TESTCASE 86 testing 185, 194–208
See also Chapter 9 See also intrusion and cache 205
and maintenance 206 benefits 187 black-box 191–192
See also black-box tests boundry value 191 cases 191
coverage 189 error guessing 191 evaluating 197 exception 191 glass-box
See white-box testing intrusion 198 memory use 202 mission-critical 186 objectives 186 performance 192 power constraint xxi random 192 regression 188 safety-critical 186 stress 191
stub code 49 unit 188 vectors 60
white-box 189, 192
See also white-box tests threads 99
time
to insight 19
to market 19, 42, 207 to money 43, 220 time-critical ISR 101 timer
watchdog
See watchdog timer timing
margin 178 specification 178 tools 38
business issues 214, 220–224 debugging 36, 40 partitioning 49
product specification 6 RTOS compatibility 34 trace
buffer 143 low-intrusion 197 post-processing 132
printf() 197 real-time 169 statements 14 techniques 140 visibility 140 traceable cache 140 transistors xxii transition board 127
translation sequence 83 transmitter buffer empty (TBMT) 94 TRAP instruction xxiv
trap vector 119
trigger 132–133, 135–137, 181 cache 141
in ICE 169 resources 133 symbolic 133
U
UART 94 virtual 123 UML 89, 106
Unified Modeling Language
See UML
unit testing 188
universal asynchronous receiver/transmitter
See UART
UNLNK 77 upgrade 18
V
variable global 86 vector 97 exception 173 interrupt 166 startup 78 table 82
VHDL 51, 53, 56–57, 62 compiler 51, 56 example 52
HW/SW convergence 52–58 simulator 60, 196
test vectors 60 video accelerator 48 volatile 91, 93, 95 VxWorks 116
W
wait states 178
watchdog timer xxi, 102, 104, 167 WDDATA 152
white-box tests 189, 192 branch coverage 192
condition coverage 193 decision coverage 192 statement coverage 192 wiggler 150–151
word size 112
List of Figures
Introduction
Figure 1: NetROM.
Chapter 1: The Embedded Design Life Cycle
Figure 1.1: Embedded design life cycle diagram. Figure 1.2: Tools used in the design process. Figure 1.3: The laser printer design.
Figure 1.5: An example of the endianness problem in I/O addressing. Figure 1.4: Where design time is spent.
Chapter 2: The Selection Process
Figure 2.1: Choosing the right processor.
Figure 2.2: Microcontrollers versus microprocessors. Figure 2.3: Dhrystone comparison chart.
Chapter 3: The Partitioning Decision
Figure 3.1: Evolution of SoS.
Figure 3.2: Another view of hardware/software duality. Figure 3.3: Where design time is spent.
Figure 3.4: Shortening the design cycle.
Figure 3.5: Hardware/software distinction blurring. Figure 3.6: Memory bus cycle of microprocessors. Figure 3.7: Conversion process.
Figure 3.8: Instructions communicating directly. Figure 3.9: Throughput calculation.
Chapter 4: The Development Environment
Figure 4.1: Memory map of processor. Figure 4.2: Subroutines.
Figure 4.3: crt0 function
Figure 4.4: Embedded software development process. Figure 4.5: Assembly lafnguage snippet.
Chapter 5: Special Software Techniques
Figure 5.1: Burglar alarm flowchart. Figure 5.2: Watchdog timer.
Chapter 6: A Basic Toolset
Figure 6.1: Storing a char type.
Figure 6.2: 16-bit wide memory storing the string. Figure 6.3: Big and Little Endians.
Figure 6.4: Typical architectural block diagram. Figure 6.5: Debug kernel in a target system. Figure 6.6: Breakpoints.
Figure 6.7: ROM emulator. Figure 6.8: ROM emulators. Figure 6.9: Evaluation board. Figure 6.10: Transition board.
Figure 6.11: Logic analyzer display. Figure 6.12: Logic analyzer data table.
Figure 6.13: Display with interleaved source code. Figure 6.14: Symbolic triggering.
Figure 6.15: Memory system diagram. Figure 6.16: Triggers.
Figure 6.17: Preprocessor connection sequence.
Chapter 7: BDM, JTAG, and Nexus
Figure 7.1: n-Wire tool.
Figure 7.2: Pinout for the Motorola BDM debug interface. Figure 7.3: Processor codes output.
Figure 7.4: BDM command set. Figure 7.5: JTAG loop.
Figure 7.6: Debug core using JTAG. Figure 7.7: Pin descriptions.
Figure 7.8: Nexus interface.
Figure 7.9: Compliance classes 1 through 4. Figure 7.10: Nexus dynamic debugging features. Figure 7.11: I/O pins.
Chapter 8: The ICE — An Integrated Solution
Figure 8.1: General emulator design. Figure 8.2: Emulation control system. Figure 8.3: Mechanical adapter.
Figure 8.4: Emulation control system.
Chapter 9: Testing
Figure 9.1: The cost to fix a problem. Figure 9.2: Memory management test tool. Figure 9.3: CodeTEST test tool.
Chapter 10: The Future
Figure 10.1: FPGA.
Figure 10.2: Gates.
Figure 10.3: Interconnecting Elements of FPGA. Figure 10.4: Worldviews.
List of Tables
Chapter 2: The Selection Process
Table 2.1: EEMBC tests list.
Table 2.2: Real-time operating system checklist. [4]
Chapter 4: The Development Environment
Table 4.1: Linker commands.
Chapter 6: A Basic Toolset
Table 6.1: Advantages/disadvantages of the debug kernel. Table 6.2: Advantages/disadvantages of ROM emulator.
List of Listings
Chapter 4: The Development Environment
Listing 4.1: Example of a linker command file. (from Microtec Research, Inc.).
Chapter 5: Special Software Techniques
Listing 5.1: UART code.
Listing 5.2: Non-reentrant function.
List of Sidebars
Introduction
Speed vs. Power A ROM Emulator
Chapter 1: The Embedded Design Life Cycle
The Ideal Customer Research Tour Flight Deck on the Bass Boat? Laser Printer Design Algorithm Big Endian/Little Endian Problem Debugging an Embedded System Compliance Testing
Chapter 2: The Selection Process
Distorting the Dhrystone Benchmark My Ideal Compiler
Chapter 3: The Partitioning Decision
Merging Hardware and Software Design Fabless Chip Vendors
Co-Verification and Performance
Chapter 4: The Development Environment
Why JMP_main Was Used Advantages of Relocatable Modules ROM Code Space as a Placeholder
Chapter 5: Special Software Techniques
Real-Time Operating Systems (RTOS) One Success Story
Chapter 6: A Basic Toolset
Debug with ISS Implementing Breakpoints Signal Intrusion
Physical Intrusion Designing for Test Other Kinds of Intrusion How Triggers Work Experiment Design
Chapter 7: BDM, JTAG, and Nexus
Hardware Instability
Chapter 8: The ICE — An Integrated Solution
Why Emulators Aren’t Used More Making the Connection
So what’s a good trigger signal? Distributed Emulators
Chapter 9: Testing
Developing Mission-Critical Software Systems Infamous Software Bugs
Dimensions of Integration
Measuring More than Statement Execution Dynamic Memory Use
Chapter 10: The Future
It’s the Fabs